@HPC Podcast Archives - OrionX.net - HPC News Bytes – 20260112

Episode Date: January 12, 2026

- CES 2026 - Nvidia Vera Rubin, in-house co-Design - AMD Helios, MI400 MI500 - TSMC GigaFab Arizona - Intel Panther Lake, 18A Fab - Sandia National Lab Neuromorphic Computing for PDE Math [audio mp3="https://orionx.net/wp-content/uploads/2026/01/HPCNB_20260112.mp3"][/audio] The post HPC News Bytes – 20260112 appeared first on OrionX.net.

Welcome to HPC Newsbytes, a weekly show about important news in the world of supercomputing, AI, and other advanced technologies. Hi, everyone. Welcome to HBC Newsbytes. I'm Doug Black of Inside HPC. And with me is Shaheen Khan of OrionX.net. The big news of late has come out of CES and at CES last week. NVIDIA maintained or actually accelerated its high-pressure chip roadmap with Jensen Wong releasing new details about the company's next-gen Vera Rubin AI chips. And this came ahead of the expected release of that information at the company's GTC conference in March. Scheduled for shipment, the second half of this year, Vera Rubin promises blowout performance delivering 5X the AI

compute of the current Grace Blackwell flagship chip. Jensen Wong also said the chip is now in full production. The Ruben platform uses, quote, extreme co-design across six chips. The Nvidia Vera CPU, Nvidia Rubin, GPU, Nvidia NVLink-6 switch, the Connect X-9 Super Nick, Bluefield 4 DPU, and Spectrum 6 Ethernet Switch. In short, it's an AI processing monster. Yeah, data Center Technologies have been getting more and more airtime at CES. It's a good thing the conference changed its branding from Consumer Electronics Show to just CES. This happened most notably in 2016 when the organization managing the show changed its name from Consumer Electronics Association, C-AE, to Consumer Technology Association, CTA, and used CES.com. Tech as its website.

In our post-Mores law era, chip choices proliferate, they fill the space between edge and cloud, and demand the co-design business model, and existing issues like cybersecurity and data privacy, and new applications like AI permeate it all. So it's a good idea to see and discuss it all in one place at shows like CES, Computex in Taiwan, CBIT in Europe, JITX in the Middle East, and maybe even Mobile World Congress in Europe and their offshoot events that aim to do that. NVIDIA's launch of Vera Rubin at CES

was also interesting, as you mentioned, because it's only two plus months away from the highly oversubscribed GTC in San Jose. So it begs the question, what else can they announce that GTC? But it's NVIDIA, and its avalanche of hardware and software will provide many options.

And customers are going to have to pick and choose, how to deploy it or where to engage as a co-design partner, if only to be able to consume it. And unless you're in a category like Google or Amazon or Microsoft, other vendors have to pick and choose where to compete. Looking at the other major chip vendors at CES, AMD's Lisa Sue gave a keynote in which she unveiled AMD's product lineup for its MI400 server GPU series and even looked ahead to the MI 500. She said the company's upcoming double-wide Helios rack scheduled for the third quarter of this year

will deliver up to three AI Xaflops in a single rack and would create a, quote, blueprint for Yada scale compute, unquote. Helios will comprise 72 Instinct MI45X series accelerators. The chip series also includes the MI 440X, a rack-mounted server with eight GPUs and one, AMD Epic Venice CPU for both training and inference, and the AMD Instac MI430X developed for sovereign AI HPC and hybrid computing. Very nice. And also very nice job skipping over Zeta scale there.

So as I have jokingly said in the past, on one side you have Nvidia who builds it all and integrates with many and says you can use the whole thing, knowing it all works together, or as much or as little of it as you want. And on the other side, you have, shall we call it, un-Vidia, which is everyone else who do not build it all, but can integrate across a wide range of options and rely on industry standards and open-source software to make up for what NVIDIA has that they may not.

AMD is obviously the leading alternative to NVIDIA and moving up the stack, now providing full systems with HILIAs and with native X-86 compatibility, their own FPGA and DPU technologies, and very competitive GPUs that are expected to be the first GPUs to support emerging industry standards like the Ultra Accelerator Link and Ultra Ethernet Consortium. As you mentioned, Lisa Sue's talk also gave a glimpse of AMD's future MI-500 GPUs, scheduled for next year that she indicated will deliver up to a thousand times increase in AI performance.

compared to AMD's MI300X GPUs. The publication Data Center Dynamics posted news that TSMC has bought a 900-acre parcel of land in the Phoenix area to expand its gigafab, which must, of course, mean that the company wants to build on its existing chip manufacturing operations of the U.S. I say that because we recall it was about two years ago. there were reports of conflicts between TSM management and American employees, along with concerns about a chip-fab skills shortage in this country. The land transaction totaled just under 200 million and will enable TSMC to expand its planned giant ultra-large fab or gigafab cluster. The publication Data Center Dynamics reported that TSM has now invested more than 65 billion

in three chip fabs in Phoenix. TSM plans to build, six wafer fabs, two advanced packaging plants and one R&D center in Arizona. While the leading edge fab technology from TSM will continue to show up in Taiwan first and then trickle down to the U.S. and other regions, the investment here nevertheless indicates expectations of high demand and the attractiveness of having substantial manufacturing capacity outside of Taiwan, albeit not the leading edge. Speaking of TSM and FABs, the latest TSM technology is its 2 nanometer class N2, which went into production in Taiwan within the last couple of months

and is a full node improvement over the 3 nanometer class technology N3 and its variants. The roadmap includes improvements to N3 and N2 nodes while pushing for A16 by late 2026, and A14 by 2028. A16 indicates 1.6, Ungstrom, etc. At this point, TSM has N3E for mass market, N3P, which is focused on performance, and it's working on N3X, which is also focused on performance and higher clock speeds. They also have the N3A for automotive chips.

InVidio's Vera Rubin family will use TSM's N3P, which is slightly better, like single-digit percentage improvements over N3E, in transistor density, performance, and power efficiency. It's been around for just over a year, so it's not the bleeding edge, which also makes it easier to use for NVIDIA. At CES, we also saw Intel announcing its new core ultra chip, which many also know by its code name Pantor Lake, which it said would be used by some 200 PC designs.

Pantir Lake is manufactured using Intel's 18A FAP, which is really the significant part of the news for us. It indicates 1.8 nanometer class technology, while it's working also on 14A, and both have been making great progress. In the chip business, yields are everything, assuming you need to make money, which is not always the case, like if you're a country focused on building a national capability like China is. But Intel does need to make money and yields for their 18A fab in urban. early 2025, about a year ago, were reported to be low, around 20 to 30%, which was not enough for commercial mass production. By late 2025, Intel's 18A yields were expected to be around 70% for Panther Lake production, and that's starting to be in the ballpark, and it can continue

to improve from there. And as it does, it is expected that it will build more confidence about 14A as well, and Intel's roadmap in general, and you need that to attract new leading-edge fab customers. So, Gene, we've been hearing about the promise of neuromorphic computing for many years, and now this past week, researchers at Sandia National Labs reported on their project work in this area that their neuromorphic systems are, in their words, shockingly good, unquote, at math, specifically partial differential equations, something that I know is near and dear to you. PDE's, of course, are the mathematical foundation for modeling phenomena such as fluid dynamics, electromagnetic fields, and structural mechanics.

Well, yes, life continues to have a lot of 3D partial differential equations, which lead to even more matrix multiplies. In a paper published in Nature Machine Intelligence, Sandia computational neuroscientic, describe the discovery of a link between a well-established computational neuroscience model and PDE's. It must have been an exciting aha moment since it showed that neuromorphic computing can not only handle these equations, but do so with, quote, remarkable efficiency, end quote. It's an important vote of confidence for a technology that tries to mimic the human brain, relying on neural connectivity and power efficiency versus brute force megawatt alternatives.

I also want to reference our conversation with Jack Dungara and some of his work on new matrix algebra algorithms. That was in episode 23 of our ad-HPC podcast, which was super popular and continues to draw listeners more than three years after our conversation with him. All right, that's it for this episode. Thank you all for being with us. HPC Newsbytes is a production of OrionX in association with InsideHPC. Shaheen Khan and Doug Black host the show. Every episode is featured on Insidehpc.com and posted on OrionX.net. Thank you for listening.