@HPC Podcast Archives - OrionX.net - HPC News Bytes – 20260622

Episode Date: June 22, 2026

- Electron-on-helium qubits - Is the new Huawei Kirin chip equivalent of a TSMC 3nm chip? - Intel launches 18A-P node, with Power Boost dual-contact transistor - Intersect360 announces market size and forecast - TOP500 analysis coming later this week [audio mp3="https://orionx.net/wp-content/uploads/2026/06/HPCNB_20260622.mp3"][/audio] The post HPC News Bytes – 20260622 appeared first on OrionX.net.

Welcome to HPC Newsbytes, a weekly show about important news in the world of supercomputing, AI, quantum computing, and other advanced technologies. Hi, everyone. Welcome to HBC Newsbytes. I'm Doug Black, and with me, of course, is Shaheen Khan. Let's start with some quantum news, quantum computing, as published in nature physics. We know quantum objects are delicate, which makes them hard to manipulate. Basically, they need to be able to tell the difference between deliberate control signals and random noise and be as immune to noise as possible. Scientists have now shown a better way to work with one of these delicate quantum objects,

a single electron floating above the surface of superfluid helium. Liquid helium is extremely clean and quiet, so it can protect the electron from many of the material defects, and noise sources that usually disrupt quantum systems. A team from Argonne National Lab and the University of Notre Dame demonstrated strong coupling between a single microwave photon and the motion of a single electron on helium using a quantum dot and a superconducting microwave resonator.

This allows them to control and read quantum information without destroying it. Strong coupling lets the quantum object and the photon exchange information fast enough that the information is not lost before it can be used. Yeah, this approach builds on methods that have already been important in superconducting qubits, atoms, and semiconductor quantum dots. It clears an important hurdle. It is not enough to have a theoretically clean cubit. You also need to isolate it, control it for computation, and couple it to measurement systems. The work is significant because it adds credibility.

to electron on helium cubits. This has long been proposed as a potentially scalable and very clean quantum computing platform, but it has lagged more mature approaches because measurement and control were hard. Electrons on helium are attractive because, as you mentioned, helium provides an exceptionally clean environment. The challenge has always been whether researchers could control and measure these electrons well enough to make them useful. This result says that path is becoming more credible.

Now, I would not say this suddenly puts electron on helium ahead of other modalities like superconducting ion trap, photonic, neutral atom or silicon spin systems. But it does move the approach from promising physics towards more serious engineering. Really nice job. WCCF Tech reports that Huawei's upcoming Mate 90 phone may use a new Kiran chip whose effective performance and packaging approach are claimed to rival TSM's 3-nometer class technology. That would be significant because Huawei and China's main chip manufacturer, SMIC, do not have access to the most advanced extreme ultraviolet or UV lithography tools for chip manufacturing. EUV is generally considered essential for economically producing the most advanced chip nodes below roughly,

7 nanometer, even if older, deep, ultraviolet tools can be stretched further through expensive and complicated multi-patterning. A couple of weeks ago, we discussed Huawei's logic folding approach and its proposed tau-scaling law. This article ties the new Mate 90 claims to logic folding, but it also explicitly cautions that the claims are unproven and that prior rumors around SMIC's ability to manufacture 5-nometer class chips without EUV have been overhyped. China continues to disclose more about its technology achievements, though it is often in ways that make a claim without revealing the details. A more defensible interpretation of the news is what we've been saying. Huawei needs to compensate for lithography constraints through

architecture, packaging, layout, system optimization, and non-standard design techniques. Of course, those same techniques can also be used by companies with access to more advanced fabs, which means China is not winning or circumventing the race as much as finding another way to stay in it. But if those methods allow Huawei to achieve similar product level performance, even just in some workloads, without matching TSM transistor for transistor, then that may be most, if not all, of what matters right now. to EUV lithography will remain hugely important and a major advantage for the US and other countries

with access to ASML chip-making technology. Yield, density, power efficiency, manufacturing costs, and scaling economics all depend on it. But if China can demonstrate a, quote, good enough and domestically controlled path, it weakens the idea that export controls can create a fixed technology ceiling. It would not mean China has caught. up with TSM, it would mean the ceiling is more elastic than perhaps assumed. But the strategic significance would obviously be larger than just smartphones. In other chip news, Intel said its 18-A process, the performance-enhanced version of its 18A process, has entered so-called risk production. The new process keeps the same design rules so customers can reuse much of their existing IP

and design flows. Intel says 18AP should deliver about 9% higher performance at the same power, or 18% lower power at the same performance, compared with 18A. In addition, customers could see between 20 and 40% improved thermal resistance and 10 to 30% improved via resistance. Vias are microscopic vertical connections that link different layers of stacked metal within a chip. The most interesting technique feature is power boost, a dual-contact transistor option enabled by Intel's backside power-delivered technology, which aims to increase current and frequency without increasing the transistor footprint. This is another confidence-boasting piece of news for Intel's Foundry ambitions and part of the series of announcements that have helped

the company's stock price appreciate significantly in recent months. Intel's Foundry Roadmap keeps getting more real. The 18A was the big jump, both in terms of note transition and introducing new differentiated capabilities like Ribbon FET for field effect transistors and power via. 18AP is the refinement that makes the platform more attractive to customers. Risk production is not the same thing as proven high volume manufacturing, but it is a critical step.

Ribbon-Fet gate all around provides a more efficient, more three-dimensional transistor structure on silicon. Instead of controlling the electrical channels from only some sides of the channel, the gate wraps around thin ribbon-like channels from all sides. That gives the transistor better control over current flow, which leads to less electrical leakage, better switching, and better performance per watt. Backside power, branded as Power Via, provides separate paths for power and signals, instead of running both through the same crowded wires, so to say. This reduces congestion, delivers cleaner power to the transistors,

lowers voltage drop, freeze up routing space, and can help the chip run more efficiently. Power boost is the new feature, as you mentioned, and as the name suggests, it pushes more current through the transistor structure. More precisely, it uses the backside. power structure to provide a lower resistance dual contact path into the transistor, allowing higher current and higher frequency without increasing the footprint. As I mentioned, this is all just a little bit more three-dimensional and more intricate in the way things are constructed.

These announcements show that Intel is starting to catch up with TSM and Samsung in terms of technology and also pointing to features where Intel has an advantage. That leaves the all-important manufacturing volume, yield, cost, reliability, and actual customer products, but it's all necessary and it all adds up. The next node, the 14A, will be until's next big milestone. Addison Snell and his crew at Industry Analyst firm Intersect 360 last week released their updated market-sizing numbers, that is, their numbers for what they call the worldwide market for accelerated, high-performance data center infrastructure. serving AI workloads. And they say this market grew by 60.1% year over year in 2025,

reaching more than $300 billion in spending. They say the AI market continues to be fueled mostly by hyperscale companies, with hyperscale AI infrastructure remaining the largest and fastest growing segment in absolute dollars. At the same time, the non-hyperscale enterprise AI market, including AI segments for HPC, reached 71.6 billion in 2025, and is projected to grow to more than 130 billion by 2030. That's just huge. AI is taken over with an impact that many people believe is as large as or even larger than the Internet. As you know, I see this as the next phase of information revolution, driven by digitization and all ultimately resting on HPC. Science, plus technology, which forms the discipline that can make sense of data.

And there will be other major phases. We're far from done. Speaking of HPC and IT, the International Supercomputing Conference is this week in Hamburg, Germany, and has probably started by the time you're listening to this. I also look forward to a new Top 500 list, and we will have our usual long format analysis as soon as the list is out there, and we've had a chance to sift through it. Stay tuned for that later this week. All right, that's it for this episode. Thank you all for being with us. HPC Newsbytes is a production of OrionX.

Shaheen Khan and Doug Black host the show. Every episode is posted on OrionX.net. If you like the show, please rate and review it. Thank you for listening.