@HPC Podcast Archives - OrionX.net - HPC News Bytes – 20260824

Episode Date: August 24, 2026

- Hot Chips, Hot Interconnects, SC26 - The Fall HPC Conference Season - Google Diversifies Custom Silicon - Industrialization of Custom Silicon - Cerebras CS-4 System - White House National Security Science and Technology Strategy [audio mp3="https://orionx.net/wp-content/uploads/2026/08/HPCNB_20260824.mp3"][/audio] The post HPC News Bytes – 20260824 appeared first on OrionX.net.

Welcome to HPC Newsbytes, a weekly show about important news in the world of supercomputing, AI, quantum computing, and other advanced technologies. Hi, everyone. Welcome to HPC Newsbytes. I'm Doug Black, and with me is Shaheen Khan. The fall HPC conference season is underway, starting with the Hotchips Conference at Stanford's Memorial Auditorium in Palo Alto. It began with tutorials yesterday and continues today and Tuesday with the main. technical program. The Hot Interconnects conference took place last week with the theme scale up, scale out, scale across, do they really differ? It focused on how AI training and increasingly distributed inference are changing the networking problem across systems and even

across data centers. And looking ahead, SC26 will run November 15th to the 20th at McCormick place in Chicago, the first SC to be held there. The overall theme is HPC Unites, bringing together HPC, AI, Quantum, and newer approaches to advanced computing, such as newer morphic computing. Yeah, I hear SC's registrations are ahead of last year this time, which is really good. The hotchips agenda is a useful glimpse of where advances are being made across processors, memory, packaging, networking, and in fact, system architecture. While tens of chip companies have come and gone, there's always interesting new developments showcased at the conference

with the who's who of the chip world in attendance. In-person registration is sold out, but they stream it online if you are interested and registered for it. Memory chips get an entire tutorial covering HBM, advanced packaging, 3D DRAM for generative inference, HBF. Risk 5 gets the other tutorial. Then we get new CPUs including IBM's mainframe class Z, NVIDIA ZVSAV-Ferra, Fujitsu Monica, arms chiplets server architecture, and Intel's Diamond Rapids. The GPU session includes NVIDIA Rubin, AMD, M.I. 400, and Intel's

Crescent Island. Tuesday adds processing in memory, CXL, computational memory, and a networking session covering Broadcom's AI-HPC Ethernet Network Interface Card and Invidio's Bluefield 4 and Spectrum X. The Hot Interconnects conference reinforced the same story from the networking side, adding Meta's gigawatt-scale AI fleet and Sienna on Open AI interconnects. Google is substantially expanding its relationship with Marvell around custom AI infrastructure. the agreement could generate as much as $120 billion in revenue for Marvell through fiscal year 233, assuming Google meets the purchasing targets associated with the deal. Under the terms, Google also receives warrants allowing it to purchase almost 59 million Marvell shares at $206.508

per share. Potentially, a stake worth about $12.2 billion and large enough to make Google Marvell's fifth largest shareholder. The work extends beyond a single accelerator. Reuters says the agreement covers processors for AI models, as well as technologies for storage and moving data across networks. Broadcom has historically been Google's main custom chip partner, and analysts quoted by Reuters view the deal primarily as Google adding another major source rather than replacing Broadcom. There was a time when building a chip meant that pretty much the entire supply chain would have to be inside one company. Then came application software for chip design and high-end manufacturing for hire, and the semiconductor industry has been on a role splitting up other parts of chip design and manufacturing.

In the process, it has reduced the cost of building your own chips, and hyperscalers and AI companies are all doing that, which is where companies such as Broadcom and Marvel come in, becoming something of a prime contractor for custom silicon and related hardware. Hyperscalers know what workloads they want to run, the economics they need, and the system level requirements. They all need complex, high-end chips, so they can accelerate their work by having a chip partner

that can co-create with them and turn those requirements into silicon packaging, manufacturing interfaces, and production. As you said, Google appears to be deliberately created, multiple suppliers rather than allowing one customer chip partner to become indispensable. That provides capacity, negotiating leverage, and architectural flexibility, and the unusually large warrant makes the relationship more intertwined than a normal supplier agreement. The broader implication is that custom silicon is becoming industrialized, expanding to more and more companies because what they have to do themselves keeps shrinking,

and the economics of it keeps getting more attractive. In a quick hardware note regarding Cerebrus, the company has launched CS4 its latest Waifer Scale AI system. A CS4 rack now contains three Waferscale Engine 3, or WSE3 turbo, wafer scale processors, mounted as plugable modules in Cerebrus's new Nexus architecture. The processors are manufactured on TSSSF, MC's 5 nanometer process, the change is primarily at the system level rather than a new process node.

The wafer scale approach keeps enormous amounts of compute on one piece of silicon, reducing chip-to-chip data movement compared with conventional accelerator clusters. Cerebra says CS4 also uses about 50% fewer components, making systems easier to assemble and deploy, while upgraded networking, improves communication among the wafer engines. The CS4 is a solid improvement, but there's two little actual specs that they have disclosed and a few claims that require sifting through. Maybe now that Cerebrus is a public company, they will disclose more information. We covered their IPO a few weeks ago. The turbo designation is not a result of a new silicon design or microarchitecture.

So there's a new system, but there's no new chip. They did manage to push twice the power through the chip that they, they had, which can double the frequency and in principle two times raw performance. Cerebrus has not disclosed the clock speed, but they did for one of their earlier chips. So people have started with that to estimate that this system could be at 2.8 gigahertz, but that's not the official number. The system architecture and off-chip subsystems are new, however. They can now put three wafers in a system instead of one, which lets them brag about a total of six times raw.

speed improvements per node, that math says performance per watt should remain about the same, but the company claims up to 10x throughput per watt for inference workloads. They've also made the system easier to deploy by decoupling compute, power, and I.O. at the rack level. Previous generations packaged one wafer and everything it needs in what they called an engine block and inside a 16-rack unit system. The new system has a common power infrastructure in the front and three independently plugable, quote, backpacks in the rear, so it's more modular. The White House has released a new National Security Science and Technology Strategy, including an updated list of critical and emerging technologies.

Policy is formerly owned by the White House Office of Science and Technology Policy or OSTP. Congress requires the strategy to be submitted following each national security strategy report. Federal departments and agencies then implemented across R&D acquisition, security, and technology policies. The revised technology list omits several areas present in 2024, including data centers, advanced cloud services, batteries, and AR-slash-V-R. additions include post-quantum cryptography, integrated photonics, 2D materials, and hardened consumer operating systems. AI priorities become more specific around interpretability, control, adversarial robustness, agent identity, and multi-agent systems. The strategy explicitly says prioritization is necessary to make U.S. technology affordable and effective.

The changes are consistent with Washington's push for public-private partnerships, focusing federal R&D where it complements what the industry is doing. Hyperscalers are already spending hundreds of billions on data center infrastructure, so government money may have more leverage in areas where private capital is not abundant yet. Since this is specifically focused on national security versus a general science and technology policy, The list gives us a picture of where government thinks future strategic leverage may emerge. Integrated photonics is becoming central to AI and HBC connectivity. Post-Quantum cryptography has moved from primarily preparing for a future threat

towards an explicit cybersecurity implementation priority, and the AI priorities have become much more concrete, including, as you mentioned, adversarial robustness, interpretability, and control. and agent authentication. So this is partly a technology list, but it is also a resource allocation framework. It influences federal R&D priorities, foreign investment screening,

research security, and export control policies. All right, that's it for this episode. Thank you all for being with us. HPC Newsbytes is a production of OrionX. Shaheen Khan and Doug Black host the show. Every episode is posted on Orionx.net. If you like the show, please rate and review it. Thank you for listening.