Grey Beards on Systems - Graybeards talk NAND & future memory technologies with Jim Handy, Director at Objective Analysis

Episode Date: March 10, 2015

In this podcast we discuss NAND and other NVM technology with Jim Handy, noted blogger (at theMemoryGuy.com, TheSSDGuy.com) and Director of Objective Analysis. Howard, Jim and I were all at Micron in mid-February to discuss their latest focus on 3D NAND and enterprise storage and we thought it would be a good time to discuss what’s … Continue reading "Graybeards talk NAND & future memory technologies with Jim Handy, Director at Objective Analysis"

Hey everybody, Ray Lucchese here and Howard Marks here. Welcome to the next episode of Graybeards on Storage monthly podcast, a show where we get Graybeards storage and system bloggers to talk with storage and system vendors to discuss upcoming products, technologies, and trends affecting the data center today. Welcome to the 18th episode of Greybeards on Storage, which was recorded on March 3, 2015. We have with us here today Jim Handy, Director of Objective Analysis, a world-renowned expert on flash storage technologies. Jim, why don't you tell us a little bit about yourself?

Okay, fine. Thank you, first of all, for having me on. I'm an industry analyst following the flash memory and the solid state drive markets and a little bit flash arrays, but not in the same perspective as you guys. Because of the fact that I come from a chip background, then I like to tell people that I look at flash storage from the inside out, that I understand a lot about the chips. I understand a little bit less about SSDs, and I understand even less about storage arrays. But I really know how the chips work and how they're manufactured that go into these arrays. And I also am very keen on the market dynamics for those. I stay in constant contact with the chip makers,

with a number of SSD makers, and certain storage array makers. So we all were at the IBM Micron event last week, and there was a lot of discussion at Micron level, at least about 3D NAND and TLC coming out, stuff like that. What's your take on what's going on in that space? It's an interesting kind of a thing. There's been an awful lot of noise about 3D NAND from Samsung. And the rationale behind that is mostly that Samsung is trying to, a leadership image by announcing this product that, quite frankly, is being built at a loss. And they're pushing themselves to ship as much of it as they can so they can get down the

learning curve faster. This kind of follows a history of things that Samsung has been doing since it entered into 20 nanometer technology. They called their process 20 nanometer class because they didn't want to admit that it was the least aggressive technology of any in the marketplace. And that caused the press to come away with the impression that they were shipping 20 nanometer devices when they were actually shipping 27. And Hynix was shipping 26. Micron was shipping 25. SanDisk and Toshiba were shipping 24. And so, you know, Samsung, even though they were on the trailing edge of the technology group,

they made themselves look like a leader. They did this again with a 10 nanometer class where they said they had had 10 nanometer class and, you know, now everybody's shipping 15, 16 nanometer products. Um, and Samsung's at 19 nanometers. They, uh, you know, decided that that wasn't, you know, the next step for them. Uh, you know, they've, they've got this 10 nanometer class, but you know, how do they maintain the solution of being ahead? And one way is to ship 3D NAND before it's ready. There are a lot of very strong challenges in going to 3D NAND. And, you know, Samsung is confronting those challenges, but I still expect them to be, those challenges to be very much in the way of 3D NAND becoming economical to produce until probably another two years or so, 2017. Before we get into the details of 3D, would it be fair to say that the word class in your business is as much a weasel word as the words up to in our business? No, I think you're understating. Oh God. Oh, okay. Yeah. So, so, so if you say,

so, you know, if I hear one X class, I should assume the X is nine. Yeah. Yeah. Yeah. Okay. And, you know, sitting, sitting, uh, out in front of my house is my daughter's 15-year-old BMW, and it's a BMW-class automobile, although its value went away about 10 years ago. Yeah, yeah. So you mentioned 12 and 15 nanometer stuff that's coming out. I mean, the discussion at Micron seemed to indicate that they were going to start shipping 19 nanometer 3D NAND, if I believe I got that correctly. Is that what you came away with as well, Jim? No. I heard it as that their current node is 16 nanometer, and that was the last planer node they were going to do.

And then they were going to do 3D. Oh. But the benefit of 3D is they don't – so think of planar as each cell as a single-family house in a suburban cul-de-sac. And when you go 3D, you don't stack single-family houses on top of each other. You build a bigger footprint. And so the cells in 3D are each bigger and therefore hold more electrons, which means if we need to keep track of the eight states for TLC, it's a lot easier. Sound right to you, Jim? There's more to it than that. And that's why we have you this is this

delving down into the details let me let me pull us back way back oh okay okay why do you scale why do you go from 55 nanometers to 45 nanometers 35 nanometers 25 nanometers you know 20 16 um the reason why you do that is to get more transistors on a silicon wafer and more on a chip. You know, basically these wafers cost, no matter what you print onto the wafers, they cost about $1,600 to produce. And so if you can produce more transistors on that $1,600 wafer, then your cost per transistor or cost per gigabyte for the NAND flash goes down. And that's the way semiconductors work. That's Moore's law. And we've gotten to a point with NAND flash where it's incredibly challenging to go past 16 nanometers in standard, what is now

being called planar technology. And so in 2007, some people at Toshiba were very worried about this, said we ought to be able to push NAND flash farther. How can we do it? And they said, well, you know, what if we take the features that we're building horizontally on the chip and find a way to build them vertically instead and put them into kind of a layered structure. And that's what 3D NAND really is. You know, I like to tell people it's just kind of you turned everything sideways. By doing that, there's the promise that they're going to be able to continue on and get more gigabytes per wafer with 3D than they were able to get with a 16 nanometer process. And once they can do that, you know, assuming that the wafer cost is able to be managed to

about the same $1,600, if they can get twice as many bits on by going 3D, then they'll end up cutting the production cost per gigabyte in half, which is the way the industry has always gone in the past and the way that they want to continue to go in the future. So even though they drop from like 16 nanometers down to 8 or 10 or something like that? Yeah, the current thinking is that it's not going to be economical to make something that is smaller than 16 nanometers, that the tools are just going to be too to make something that is smaller than 16 nanometers that the tools are just going to be too expensive and that you could make a 14 or a 12 nanometer nand flash and 12 12 appears to be the limit of possibility today but you know there are always these geniuses who come out with

ways of pushing it farther but you could make those but they'd end up requiring enough expensive tooling that you wouldn't be able to make a $1,600 wafer. You'd make a wafer that had twice as many chips on it for $5,000. And, you know, that just doesn't make economic sense to, you know, get twice the transistors and be paying three times as much for the wafer. So that $1,600 number is including all of the processing steps? Yes, it is. As a matter of fact, it's a processed wafer, and a lot of that cost, roughly 50% of the cost, is capital depreciation on the tools, which you're probably not talking to an audience that worries about things like that. Your audience is a lot of accountants. But the basic deal is that if you buy a $100 million immersion stepper, which is what some of these tools actually cost,

then you've got to pay for it somehow. And the more chips you process on that tool, then the cheaper your costs are. But if I understand the way this all works by going 3d i mean essentially we're doing multiple you know each layer has to get laid on by one of these machines so if instead of running you know 20 or 30 layers to get one cell in a planar technology, if I'm going to get 16 cells stacked up, isn't that going to mean a lot more of the amortization on that machine goes into that wafer? It sounds like that, and that confuses an awful lot of people. A lot of people think of NAND 3D as being that you process a layer, you know, and do lithography on it,

and then you process another layer with lithography, and then you process another layer. It's not like that at all. And I actually wrote a series of blog posts that are a little deep, you know, it might be slow going to read through that for your audience, but you know, if they want to, it's there. It's on my blog called The Memory Guy. It's just thememoryguy.com. This is what I get for only reading TheSSDGuy.com. Yeah, well, TheMemoryGuy.com explains in maybe painful detail how you make 3D NAND. Let me give you the 20-second review of that. And that is that with 3D NAND, you decide how many layers you're going to make you

know let's say it's 32 layers and you put down 32 layers kind of like you'd make a layer cake um on this whole wafer you know and so it would be cake frosting cake frosting cake frosting 32 times and then you bore holes into it and then you fill those holes with a kind of an elaborate structure that is shaped like a bunch of concentric columns. And all of a sudden you've got the NAND flash string that you'd have, you know, by processing sideways or, you know, horizontally on a regular wafer. Now, that boring the hole is the only step that requires lithography, where you have to pattern something, you know, using visual patterning. And so because of that, if you lay down 32 layers and then bore a hole, it costs the same thing in lithography as if you lay down 64 layers and bore a hole, like 128 layers and bore a hole. Ah, okay. Lay down 128 layers and bore a hole. It's the same boring hole cost.

Okay. Okay, so the actual putting the layer, the additive steps are across the whole surface. Yeah. And just that subtractive step. Oh. Is in a particular place and requires a lot more effort and stuff like that. Oh, that's interesting. That means it's going to scale a lot more effort and stuff like that. That's interesting.

That means it's going to scale a lot if it works, right? Well, yes and no. One of the problems is that today's devices use a hole that is 40 times as deep as it is wide. It's got an aspect ratio of 40 to 1. And that's with 32 layers. Actually, that was with 24 layers. I think the 32 layer is actually more than that, like close to 60 to 1. And that's pushing the limits of technology being able to do a 60 to 1 aspect ratio whole. When they go from 32 layers to 64 layers, then they're going to have to double that aspect ratio. And when they go to 128 layers,

then it's going to have to be four times the aspect ratio. And when they go to 128 layers, then it's going to have to be four times the aspect ratio. And it's really tricky to make a hole that is, you know, let's say it's 240 times as deep as it is wide. And make sure that it's really... And what?

20 nanometers across? No, actually, they're using these things that are about 70 nanometers across. Yeah, huge. Yeah. Yeah, comparatively. Yeah, you think about that. Let's say if you went down to the hardware store and bought a quarter-inch diameter dowel that was 32 inches,

that's about 120 aspect ratio, 120 to 1. That's huge. Yeah. It's not so difficult to make a dowel that is shaped like that, but try making a hole that's shaped like that. Yeah, yeah, yeah. Because now, even if we're talking about that really long drill bit and I need it to not whip around any yeah because the hole actually ends up getting bigger if it whips around yeah yeah and at 70 nanometers you can't use a laser because you're well below the wavelength of the lasers yeah they they use something that's called dry etch

um it's it's a combination of microwaves and reactive chemicals where you you know get get something that that likes to eat silicon and then you get excited by bombarding it with microwaves and reactive chemicals where you you know get get something that that likes to eat silicon and then you get excited by bombarding it with microwaves and it burns these holes in and then then the question is what do you do with the ash that results from that it's hugely complicated you can't just turn it over and dump out the ash in a can and stuff like that and take it away i guess yeah you tap it three times on the but you know when you got little tiny hole stuff sticks in there anyway yeah oh yeah and and you know another thing that's a problem with this is that they they make all those holes they also um dig these trenches between uh pairs of holes so they've got these you know very vertical

it's kind of like a comb structure. And they have to use what's called dry etch, use this chemical process that I was just talking about, because if they tried using wet chemicals like liquid acids, which they use in a lot of other semiconductor processes, then you end up with the capillary effect causing there to be tension between the two prongs of the comb, the two teeth of the comb, and it draws them together. And because they're so small and so close to each other, they get stuck, and they can't get unstuck from each other.

Oh, my God. Aren't you glad you're not a semiconductor guy? Yeah, yeah, yeah. It opens up a whole new dimension here, so to speak. This is why I gave up chemistry. Yeah, yeah, yeah, yeah. Yeah. Thank God.

But, you know, the deal is with any semiconductor process, doing the first one is hugely complicated. Yeah. And doing the next 10,000 of them is a lot easier. And then, boy, once you've done 10,000 of them, then you can do it in your sleep. Yeah. Right. Kind of like software. Yeah, kind of like software.

Yeah, maybe so. Doing the first product is significant, but making 10,000 copies is trivial. Well, making copies is trivial. That's why we've got copyright laws, too. Yeah, yeah, yeah. Okay, so Micron seems to be pushing 3D again for the next generation, I guess, after their planar solutions, they come up. The other thing that was surprising to me was the push for TLC. It always seemed to me that TLC and MLC had worse endurance than SLC. I think MLC, you know, went from like 100,000 to roughly 10,000 program array cycles.

I'm thinking TLC would take that down another notch. Is that your belief, Jim? Yeah, and, you know, that's something that the semiconductor industry has been talking about for a long time, is that TLC could actually get down to the hundreds of cycles before you end up with wear-related issues. You know, there are a few things to keep in mind about that. One is that when you start losing bits, it's not like you get a catastrophic failure. It's actually a bit will disappear here, you know, and become unusable. It's, you know, not like it just vanishes, but you get a bit that's either stuck in a one-state or a zero-state, and then a few more cycles and another bit will end up sticking in one state or the other.

But the semiconductor vendors actually set the bar really low for wear with the wear that they'll guarantee. Because if they had to guarantee it, they'd have to do a lot of testing, which is extraordinarily time-consuming tests. They would rather do the tests that they can do quickly and not spend a lot of time doing tests that take a long time to accomplish. These tests might take weeks or even months. And have to be done on a significant percentage of the wafers and stuff like that, right? Yeah, you know, even if you only tested one dye per wafer for this test, if that held up your shipping the wafer for a month, that would be a problem.

So, you know, these guys want to be able to ship. And so what they do is they just set a very, very conservative target for themselves as to what it is. You know, it's the worst specification that the customer will still accept. Typically, though, the wear on a real device might be an order of magnitude or two orders of magnitude better than what the NAND makers say that it is. A lot of, well, not a lot, maybe half of the SSD controllers and certainly the enterprise SSD companies, they take advantage of that. They say, okay, we can either use the manufacturer's specification and decommission anything that's had 10,000 race-write cycles and just say it's bad

without checking it out. Or we can look at it and actually see what the behavior has been over time and whether or not the same bits have been sticking. And a number of enterprise SSD makers do that, and they find out that they're able to take advantage of this extra order of magnitude or more of wear and make the things wear longer than what TLC has specified to do. One of the enthusiast sites, I think it's Tech Report, took a dozen or so SSDs and decided to keep writing data to them until they died. And the Intel SSD, when its smart counter reached zero, so when it used the guaranteed amount of read-write cycles on the flash, stopped accepting new data uh because that's how their controller was

programmed was like you can do 3 000 cycles and when you're done we're not going to go past that because it would be dangerous some of the other guys went 10 times what you should expect before dying so due to their ability to try to take advantage of this phenomenon yeah and you know there there is a caveat there for your listeners and that is that um you might buy a bunch of ssds one year one day whatever and find out that they all run you know however many uh race right cycles you know the 10 petabytes or something like that, way beyond where they're expected to. But don't count on that because it could be that you buy another batch on another day

and they end up only doing three petabytes. Right. So there's a lot of variability. Yeah, there will be a lot of variability. Well, especially with consumer SSDs where we see that vendors who aren't attached to foundries will change components without changing model numbers. Yeah, yeah. Or even the day-to-day changes within a single flash manufacturer can make that change. It could be that the flash manufacturer finds out that if they do a speed tweak on the design of the part that they're able to sell parts into markets

that they weren't able to sell into otherwise. And so they just implement the speed tweak on every chip that comes out. But that speed tweak may end up having some consequence to the endurance that, yes, it still passes its 1,000 race right level or whatever that number is. Right.

But the old version used to do 2,000 and now we're down to 1,200. Yeah, exactly. Yeah, yeah, yeah, yeah. And since we only guaranteed 1,000, we don't have to tell the people because we're still better than the guarantee. Yeah, exactly. So what are SK and the Toshiba SanDisk teams doing about 3D? I haven't heard anything from them.

Oh, actually, SanDisk has been very vocal about what they're doing, and they've got a completely different approach than Samsung does. SanDisk and, you know, Toshiba pretty much follows SanDisk's lead. So what SanDisk is doing is... Oh, wait, wait, wait. Hold on there, because that's a much more interesting topic. So on one of the storage field days, we went on a tour at SanDisk. God, they were great. And everybody was very impressed at all of the chip-level microscopes and stuff that was around there, even though that facility wasn't literally attached to a foundry.

So are you saying that SanDisk actually drives the R&D for that consortium, as opposed to Toshiba driving it? Everything they do in chip manufacture, they do together. Right. From controller technology standpoint, they're two very separate companies. Yes. From a NAND chip manufacturer, they design chips together. They do chip R&D together. And the chips that are made in their joint production facility all have both companies' names on them.

Okay. So what they're doing in R&D, they do together. And Toshiba is very, I don't know, they don't say an awful lot about what they're doing. And SanDisk is very forthright and explains what they're up to. And SanDisk has said that they're not going to enter 3D NAND production until they see a clear path to a better return on investment from 3D than what they'd get from their current planar technology. Okay. So, I mean, do you mean that as we're just not going to ramp up until we can actually

make the new stuff cheaper or that we're dedicating more R&D to another planar cycle? Um, well, I do believe that they, they have, uh, you know, under wraps, um, another planar ship that they're trying to figure out how to do. And I think all of the NAND flash manufacturers have that, um, you know, to get over this problem I mentioned before of the $5,000 versus a $1,600 wafer. Um, but, uh, you know, they But what they're disclosing about what they're doing is that they are working on 3D and that their plan is to only make 3D when they believe that there's a path for production 3D to be cheaper than their production planar devices. Yeah, yeah. Okay, we've been getting into a lot of the current NAND technology

and its next steps and stuff like that. What's after NAND? Because, I mean, there was a brief discussion at Micron. He flashed up a slide that had like six different technologies and said, these are all potential after NAND solutions to the same sort of storage problem. Where is that going? And what's the horse race there, Jim? I like to call a lot of those things the technology of the future and destined to stay that way.

Oh, holographic storage. It's always five years away. Yeah, I like that um these the first time that i ever heard of one of these technologies threatening another technology was um back in the late 1980s when ramtron uh was talking about displacing all existing memory technologies with a non-volatile technology that was going to be as cheap as DRAM, lower power than SRAM, and non-volatile all at the same time. There are a lot of candidates for technologies that are going to replace NAND flash,

but they're not in a position where they're likely to do that anytime soon. You know, a lot of the problem with just NAND is the cheapest thing you can get from a semiconductor memory standpoint. It costs a twentieth as much as DRAM. And, you know, it's hard to get beyond that. And it also uses silicon and no exotic materials. And, you know, that's something that also pushes up the cost of the wafer, is once you start putting some other material onto the wafer, then the wafer cost goes up significantly, mostly because people don't understand how to use it. You know, about $300 billion have been invested in silicon R&D to date over the history of the

semiconductor industry. The process technologists really know how to move those silicon atoms around and how to make them do their bidding. And they don't really understand the other materials quite as much. But to get back to your question, what is going to happen? I've been taking the position that it's unlikely that we're going to see one of these new technologies supersede NAND flash until we've seen Planar run out its entire life, which I'm expecting to go into 2017, and then until 3D does three or possibly even four generations, which if each one of those takes two years, you know that would take us out another six years and uh so you know i'm saying that 2023 is when we're likely to see these new technologies actually start to displace flash hp talks about memrist are coming out eminently and all that stuff. Yeah.

And, and, and M Ram and, and re Ram and, and those sorts of things, you know, I think M Ram is actually shipping and, you know, small capacity.

A lot of those things are shipping, but they're like, you know, eight megabyte chips, not, not eight terabyte chips. I was going to say 16 meg, but who's counting?

And the, the two companies that are farthest along are probably companies that you've never heard of. One of them is Everspin. Yeah. So you do know them. The MRAM guys, right? Yeah.

They have a one megabit part. That they shipped today. The current NAND is, I'm thinking, 32 gigabits? Is that? There are 128 gigabits. Oh, God.

All right. Yeah. Yeah. So, you know, we're way far away from a megabit. And, you know, you think about that, and you'd have to make a really really small one megabit mram part to to be able to fill up a wafer with as many bytes as you get building 128 gigabit man flash chips yeah no um so we're not there but you know it's it's got its market niche and uh you know it's doing very well with that um but then the other technology that is out there is from a company called Adesto, and it's a metal ion technology,

which some people would call a resistive ram, where these little silver bridges form through a piece of glass and either conduct if the silver bridge is there, or you can evaporate the silver bridge, and then it doesn't conduct. I got a briefing from those guys. That looked like really fascinating technology, but to scale that down to a two nanometers size. It has the promise of doing that. And also these technologies have the promise of being able to be layered so that you can build many bits the same way that you do 3D NAND.

So, you know, there's a roadmap to get these technologies cheaper than 3D NAND once 3D NAND reaches its limit. But, you know, it's not clear today what the limit is for 3D NAND. You know, back on the TLCc thing too yeah yeah yeah and and you know something that i wanted to point out is that the um technology for for managing nand flash has actually moved ahead at a pace that is faster than the pace at which NAND flash is getting bad. So the controllers actually, today's controllers, make today's TLC NAND flash behave better than SLC NAND flash performed five years ago with controllers from five years ago.

You know, it's an interesting... I realized that the controller technology was moving forward very quickly I hadn't realized it was quite to that extent and if you take that to it's logical extreme someday we'll end up with controllers that are so sophisticated

that they'll take completely non-functioning NAND flash chips and still pull out good data isn't that the Facebook approach? going with bad SSDs and populating with cold storage? Yeah, they want that. And that's another thing that I wrote on the Memory Guy blog was I had this post called Why Facebook Can't Get Its Dream NAND Chip.

And the reason why is because there just isn't anything that you can do to take more cost out of a NAND flash chip. The guys who currently ship NAND flash are doing just a phenomenal job of getting the cost out of these things. Yep. So the current chips, which are way too good for Facebook, are as cheap as you can make them anyway. Yeah. Lovely. Something interesting, though, that somebody from Sandforce presented was, he said, how compressible are things? Because Sandforce's SSD controller actually compresses the data before it goes into the NAND flash. Yeah.

And he said that HTML can be compressed on average to 17% of its original size. Yeah, because text. I mean, effectively, it's all text. And most of it's uppercase. Yeah, yeah, yeah. Well, you know, we all have gray beards. I'm old enough to remember when Dex stored text in six bits, which didn't leave room for lowercase

well bodo code is five yeah but there's the shift characters yeah yeah okay and i want to make sure that if there are any programmers listening to this that it's on them not to document their html because documenting it takes up room on the flash and No doubt. No doubt. No doubt. That's interesting. The one thing I think our listeners really don't get is how the lines between SLC, MLC, and TLC are blurring nowadays. I know Micron, you can take one of their flash chips and say 10% of the pages

are going to behave like SLC, and the rest of the pages will behave like MLC. Can you talk about that a little and about what that means in terms of endurance? It seems to me like I'd write my controller so that those pages were the landing zone and then garbage collect the data out the same way we use Flash to keep IOPS away from spinning disks. Yeah, and that's a tiering or some kind of a hierarchical way of doing things. Just in case anybody on the call doesn't really understand the differences between SLC, MLC, and TLC, the individual bit storage on any DRAM or NAND flash is kind of like a capacitor that you store a voltage on it. And in typical DRAM or SLC NAND flash, you either store a high voltage or a low voltage. And if it's, you know, above the middle level, then it's a one.

And if it's below the middle level, then it's a zero. Somewhere along the line, somebody got clever and said, hey, we can's a third, anywhere below a third of the maximum voltage is one, anything above two or between two thirds and one third is two. And anything that is above two thirds would end up being a three or yeah, three. So, so you've got these, you know, four voltage levels, zero, one, two, three. Same with storing three bits is that you end up just with eight levels instead of four levels. And at some point, you end up with these differences in voltage that are small enough that the noise on the chip makes it very hard to distinguish between one and the other. To do that, to be able to sense the differences between voltages on these things slows down how quickly you can read because you have to wait for these very long settling times.

What? What? Settling? Voltage settling? Yeah, yeah, yeah. You know, it's just a noise problem if there's a lot of it's just like the head settling on a disc it just takes a lot faster oh god yeah so it's it's the same kind of thing you're right i hadn't thought about that and then writes also take longer because you're writing these you know mysterious and stuff like that? Do you have to...

Yeah, you write and then you read back and then you nudge it a little bit in one direction or the other and then you read back. So on MLC, you want to write the voltage level that represents a 0-1 and you try and then you read it

and you see if you got that and you adjust it. But because SLC, the difference between a 1 and a 0 is so clear, you can just hit it once and not have to go through that cycle. So that's why the writes on SLC are so much faster. Yeah, and on 3 bits per cell, you're going to end up having to do a lot more writing and sensing, because you've just got a whole lot more voltage levels that you're trying to manage on there. So it ends up being slow to write. It's slow to read because of the settling time. But also the mechanism that causes flash bits to fail is that the capacitor becomes leaky. And so naturally, the more voltage levels you store on a cell,

then the more sensitive you're going to be to leakage in the capacitor. You know, it's... Right. If one electron puts up a poster of Raquel Welch and digs a tunnel behind it... Raquel Welch, you are oil. Wait a minute, I think I just saw that film. What was that? Shawshank Redemption. Yeah, yeah, yeah. Oh, well, you are old. Wait a minute, I think I just saw that film. What was that?

Showshow Production. Yeah, yeah, oh, God. But if it's... So you got the hots for an old lady. Well. Well. Anyway. I appreciate a fine piece of cinema.

And ain't none of us spring chickens. I'm sorry, Jim. Go ahead. You were talking the technical side. Okay. So, you know, you've got TLC behaves worse than MLC behaves worse than SLC. Now, because of the fact that all of these bits are the same as each other, they're just being written different voltages. People who understand

what's going on inside the chip, which is basically the chip manufacturers, um, they, they have the ability when they're shipping the chips to say, okay, this chip, the chip's going to be an SLC chip. And they modify, um, uh, fuse inside that chip that says, okay, this chip's going to be an SLC chip, and they modify FUSE inside that chip that says, okay, this is an SLC chip, and they say this chip's going to be a TLC chip, and just sort them out that way. But also, if they're making SSDs, then they can make an SSD that reassigns pages within the NAND flash to be either SLC with its faster read and write or to be MLC that's slower or TLC that's even slower. Within the same chip? Yeah within

the same chip. So they're not fusing here per se. Yeah. There's some sort of programming programmable nature of it I guess right? Yeah and it's just another flash bit you know you have a flash bit that says, here's what we're going to do there. There are an awful lot of adjustments that are trimmed by actually setting a linear voltage inside the chip. And all of those adjustments are done

by using a flash cell. And so if you have access to that flash cell, then you can change what the program settings are inside the chip. It's kind of like a meta flash cell, then you can change what the program settings are inside the chip. It's sort of like a meta flash cell here, powered. Yeah. You know, we moved, you know, basically we moved the BIOS from a ROM to a flash chip, and now we can change it when we need to.

Yeah, yeah, yeah. But this is kind of where the SSD vendor who has vertical integration, where SanDisk, who knows the details about what those flash chips does and gets to tweak the controller to say, you know, our flash chips will let you do 15% SLC and you can change that anytime you erase the whole chip as opposed to the micron chip, which acts just a little bit differently. You can start where they only let you change the settings once before you write data to the chip in the first place. Both examples pulled completely out of my head. I did not read the spec sheets. But there are very flash chips at that level that give the vertically

integrated operator the ability to take advantage of those tweaks. Alright, so it's almost the end of the call here, so I have one last question, Jim. HP's been talking about Memrister technology for, I'm thinking, five years now. And I actually saw something that said that it's likely to have something in the Memrister technology for, I'm thinking, five years now. And I actually saw something that said that it's likely to have something

in the Memrister solution set here coming out within the next year or so. Is this resistive RAM? Whether it's resistive RAM depends on who you ask. But my understanding is that it behaves pretty much like a resistive RAM. If it walks like a talk and quacks like a duck, it's a duck. And that predates me. I never did see that TV show. Okay.

But, yeah, it was the $64,000 question or whatever it was, Groucho Marx. Yeah, yeah. You bet your life. Yeah, you bet your life. Anyway. Give you a cigar when you say the magic word. Word. So my understanding from talking to the guys at HP is that this product is actually going into a system that I believe the initial prototype is going to be released this year that is called

The Machine. Yeah, yeah, yeah. I believe that you need to add echo to my voice when I say that. Yeah, okay, I'll see if I can do that to the editing process. We'll run you through Auto-Tune, take you down and off you. What the hell is The Machine going to do? It's not storage. No, it's a computer, but what they plan to do is to completely rewrite computer architecture,

and part of it is to make the memory the same as the storage. And so the Memorister is going to be used for both memory and storage in this machine. Okay, well, I mean, that's the goal, right? Isn't that the goal ultimately of all this work we've done? Ever since I was in a tape system working on tape,

everybody really wants their data in memory, but they're not willing to pay the price. So that's why all these storage technologies came into existence. And if you can actually create a big enough storage in memory, you don't need storage as long as it's not volatile. Yeah, you know, the sticky wicket here is just what it costs.

And there doesn't seem to be a path to bring memory costs down to the level that's attainable by storage. And it just doesn't look like it's ever going to happen. And so because of that, we'll still have hierarchies. Yeah, and I.O. and all that stuff. Although the concept of some of these newer memories

that are much more symmetrical than Flash being used, even if it's a tier of memory, but just directly addressed by the processor looks really attractive but i think i think we're 2022 2023 before it becomes viable you know it'll be viable for those applications and niches before it's viable for storage but still a long time out what's what's fascinating to me is how little anybody is doing from a computer architecture standpoint to take advantage of NAND flash as being a cheap and nasty memory layer

instead of being storage. That was one of Diablo's pitches, that you could take those flash dims and map them directly into the memory space and run something like hana on them yeah um yeah but of course now we have to wait till litigation gets resolved to see to see if that becomes a viable alternative yeah yeah okay well i think we've reached about the end of the podcast. Howard, do you have any final questions? No, I think we covered it.

Oh, wait. I do actually have one final question. Jim? Yeah. Do you have any idea what SanDisk actually announced this morning? Yeah. As a matter of fact, I sat in on the announcement. Do you want me to talk about it now?

Sure. Okay. They have a box that has got a gob of flash. It's 512 terabytes in 3U. And it's got 8 SAS connects. 512 terabytes in 3U?

Yeah. Does it sound like Skyera to you? Yeah, it could be. A little bit, but I think the SanDisk guys are a little more credible than Rado. Yeah, maybe so. But then the question is, is this something that the market wants and needs? Right.

You guys would probably be better. Did you say it had eight SAS connections? Yeah. Okay. This is testing the limits of my competence here because i'm a chip guy and i don't know whether this is a useful combination i i find it i find it hard to think of of mainstream use cases where i have a petabyte of flash you don't think sas connected to up to up to eight servers. What do you think DSSD is?

I think DSSD is an RDMA connection into the server. Rather than SAS. Yeah, because, I mean, look, if you get, I mean, think about the average data center. If you're talking about half a petabyte of storage. That's a lot. That's everything. You're going to put that, you know, you're going to put like SVC or Falcon Store or something between a SAS. That goes back to what Texas Memory Systems used to do. It's a rack-mount SSD more than it is a storage system.

I can't run my VMware cluster if I've got that much storage. It's way more than eight servers. So, yeah. Yeah, it's an interesting project uh they did also what sky era does of um you know making a big deal about the cost and they said that where um a lot of competing systems have costs that are 10 to 12 dollars raw storage and then when it's compressed it gets down you know gets down something less than that, like $4 or something like that. Theirs starts out as $2 per gigabyte raw

and under $1 compressed and deduped. This is amazing. Are they doing the compression and the dedupe, or are they saying that you could do that externally? They didn't make that quick. And it's available now? saying that you could do that externally. They didn't make that quick. Wave hands at it. And it's available now? Yeah. Oh, my God.

It's interesting just because it's a continuation of the collapse of the storage business where the component vendors and the system vendors, the lines are blurring. Yeah, yeah, that's true that you know five years ago i mean even three years ago people were asking me you know why doesn't emc make their own ssds for their server for their host side cache software and i said you know their system vendor there are component vendors and never the twain shall meet. But since then, the twain have met quite a bit. HGST today announced they were buying Amplidata in the object storage space. And we're just seeing more and more of the

component guys trying to move up the stack. The whole Micron discussion was moving up the stack, I mean, to some extent. Oh, I was just going to say that Micron, you know, their big announcement with the Seagate thing was that they're going to be a SaaS SSD supplier as a result of that. Yeah, there you go. I continue to believe that that team that they put together at Micron is designed to sell bigger things than SSDs. But apparently nothing we're going to see in the short term. Alright, I think that brings us to the end.

Jim, is there anything else that you might want to mention? Oh, I could talk all day. I know, but you have like two minutes. No, I just want to thank you guys for having me on and count me in as another gray beard. I remember Raquel Welsh.

Yeah, we all do. Fondly. Well, this has been great. Thank you, Jim, for being on our show. And Howard, thanks for being on the call. Always a pleasure. Next month, we'll talk to another startup storage technology person. Any questions you have, please let us know.

That's it for now. Bye, Howard. Bye, Ray. Bye, Jim. Bye, Jim. Bye, Ray. Bye, Howard. Next time, thanks again.