In The Arena by TechArena - The Future of Semi Innovation from Disruptive Memory to Chiplets with Alphawave Semi

Episode Date: March 30, 2023

TechArena host Allyson Klein chats with Alphawave Semi’s Letizia Guiliano about the future of semiconductor innovation across memory, optical and interoperable chiplet solutions and how her company is poised to deliver leadership innovation rooted in standards.

Welcome to the Tech Arena, featuring authentic discussions between tech's leading innovators and our host, Allison Klein. Now let's step into the arena. Welcome to the Tech Arena. My name is Allison Klein, and today we're coming to you from MemCon in Mountain View, California. I'm here with Letizia Giuliano, Vice President of Product Marketing at AlphaWave Semi. Welcome to the program. Thank you. Thank you for inviting me. Why don't we just get started with an introduction of you, your background, and your role at AlphaWave Semi? Of course. Yeah. So again, my name is, you said it perfectly, Letizia Giuliano, Vice President for IP Product Marketing and Management here at AlphaWave. Me and my team are responsible for IP solution for our SLC customer and custom silicon as well.

We mainly work on high-speed interface connectivity and chiplet design. AlphaWave has a very broad silicon portfolio. It's quite expansive. When you look at what you're offering in the industry, can you talk about the markets you're serving and how you're prioritizing the products that you're delivering for your customers? Yeah, so here at AlphaWay, we are leader on high-speed connectivity, and we base all our offering on our core expertise that are DSP-supposed servers.

And the market that really takes advantage of that are definitely high-end markets like high-performance computing, data centers, and servers. However, some of our DSP technology can also be scaled down for different types of applications like SSD, storage as well, when we think about PCI Express and CXL. And also we expand that application to optical. So we have a product line of optical products based on DSP as well.

We also give the chance to our customers to use our IP in more custom silicon solutions. So we offer custom silicon solutions in the form of ASIC or SoC engagement, thanks to our leaders on ASIC design, packaging technology, and taking advantage of the latest TSMC technology or funding technology. We're at MemCon today, so memory is the topic. How do you see the memory arena evolving in the AI era? And what is driving the demand for changes to memory?

Yeah, so it actually was interesting this morning. We heard some talk from Microsoft and Samsung. And for me, and based also on my background, what we're seeing with our customers, the major takeaways is AI is a new way to use non-traditional memory for other stuff. So we have these new needs of a different type of workload that don't require just one single type of memory. But you need to segment that in different type of workload that don't require just one single type of memory, but you need to segment that in different type of tiers. I think there was a Samsung talk talking about tier of memory.

So you have memory close to your system like cache, but you have HBM, for example, to give you another type of access to memory, distance closer with higher bandwidth and lower latency. So I think AI is really stressing a new non-traditional way we're using memory interface that is a mix between how data center was using it and server we're using and GPU take advantage as well. So it's a mix of all this technology put together with a more inventive way. What you've described is really a reimagining of the entire memory storage hierarchy into

a memory hierarchy. I know that you're showing a number of HBM solutions at the show. Can you describe where HBM specifically is in that memory tiering and where you see it showing up in the marketplace? So HBM, high-banded memory, is a new way of using DRAM technology for a faster, closer to your SSE. So HBM is based on a 3D stack technology, so it takes advantage of new processes like TSV through Silicon BIOS and 3D packaging and allows SoC to have a wide parallel bus, faster and higher bandwidth. Differentiated from other types of traditional DDR memory like DDR5 and DDR6 because it allows

you to have higher bandwidth with lower latency. And so definitely a data center, AI and machine learning, can take benefit of HPM and boost those type of workloads that require high bandwidth memory. How is AlphaWave leading in this space? And what kind of collaborations are required to deliver the core capabilities that you've described? AlphaWave is leading on everything that requires high speed interface, take advantage of our expertise of designing higher data rates, IP and five for a more reliable solution. So we work with our teams. We have a good ecosystem in terms of packaging design. We have a team of packaging design as well that are able to really make sure that our technology is tested across every type of channel. Also, we have a really good relationship with the ecosystem in terms of industry standards and partners. We work a lot with JEDEC, IEEE, or ODSA and our customers

to make sure our solutions meet their type of needs. It's also possible collaboration with foundries as well and memory vendors. They're looking at us to test what is going to come next and making sure we provide a reliable solution to our customers. You mentioned CXL and CXL has certainly been a huge topic in the industry as well as MemCon this week. Now that we have platforms from both AMD and Intel featuring CXL, and we have specs from the consortium all the way through CXL 3.0, how do you see this rolling out over the next few years? And what do you expect in terms of the types of youth cases? Okay, so CXL today and ReadWeb is CXL 3.0, one of the latest standards, is based on infrastructure, T-Species, PCI.

So CXL 2.0 is based on PCS-Presidient 5 and CXL 2.0 is based on PCS-Presidient 6. I do think that T-L Gen 6 provides a boost in data rates, but it's not enough for the bandwidth that this type of system will require. So we come back to my previous point where SoC designer and SoC architect need to start partitioning their system and having alternative memory access.

So CXL may be one of them, but will not be the only one. They also need to still have access to that type of tier of memory like HBM or DDR5. I think CXL could provide benefit for some type of workload, but still will require access to different type of memory interface like HBM and DDR5. When you look at the opportunity for AlphaWave in the market as someone who provides so many different types of technology solutions, who were the critical collaborators for you to get to the point that you're at today? And how has the opportunity changed for multi-semiconductor collaborations? So I think our main partners definitely are foundries and packaging house. Our technologies so interleave together. When you design high-speed interface AP, we are the IEOs to the package. We are the

interface to what is coming outside. So for us, it's really important to have a good ecosystem that puts together what the foundry does in terms of silicon and semiconductor with what the package technology provides. So definitely foundries, packaging house, and the new way that the packaging is also evolving to take advantage of a high-speed interface. It's really important for us to put it all together. So we bridge all those expertise together. The next, I think, other important partners for us are our customers. We see them more as partners than customers. We are like one single team trying

to solve the big next thing. So they are definitely a good portion of our ecosystem and enablement. Yeah, and definitely industry standard. I mean, having forums where we are all active and we participate to big problems in in a more pragmatically way like interface for die to die everyone we participate and we take leverage and building new idea accelerating also introduction to standard in the market you brought up one of my favorite technology standards which is ucie so i've got, yeah. I'm going to ask you some questions. Yeah. This is an incredible opportunity for innovation and a different way for silicon vendors to

work together. What is your vision for UCIE and how long do you think it's going to take to start seeing UCIE-enabled products in the marketplace? Oh, I like that question. It's my favorite talk these days. I talk more about UCI than service. So I think that definitely there is a need to disaggregate our system. Monolithic solution doesn't suit anymore, especially for the market where we play.

What we're trying to do with the UCAE standard is start to build an end-to-end solution that provides not just an electrical PHY compliance, but also protocols that compliance. So I think there has been a lot of work went in the electrical. I mean, we are engineers. We like to solve all those problems. There is a lot of work that went in the protocol, also thanks to PC Express, CXL, and other type of streaming protocol. Now the next big thing will be to resolve how all those things are going to get together in a platform that can be used for interoperability. So that, I think, is the challenge for UCI and the challenge for who participate to the

working group and to the industry to try to find a way to make this problem simpler and create a platform for people to use. So right now, we have a lot of examples in the industry of UCI-like interface for big companies like Intel. I was part of the Ponte Vecchio team where it was a big example of integration and disaggregation. Now we need to find a way to leverage that expertise to build an open ecosystem. Let's just say when you look at what you've just described, you've talked about new memory tiering. You've talked about CXL being forced to increase memory tiers in one way. And then you've talked about the Universal Chiplet Interconnect Express enabling just unfathomable interoperability between chiplets in a package.

When you look out five years, how do you imagine the semiconductor industry using all of these technologies and standards to deliver new core capabilities for data centers? And what are you most excited about for AlphaWave being part of that leadership? I think I heard this one, someone said that the package is going to be the next motherboard. And I really relate

to that. This is my son, I have to say, yes. And AlphaWave can build a lot of pieces inside that package to make sure that we accelerate time to market for this solution. So as like the motherboard, right, you will buy standard part that can be bolted together, a memory part or a retimer and things.

Then Rafaway can provide those components already silicon proven and ready to integrate for accelerating the solution and things are going to be also providing a flexible business model for that as well as also a reliable system solution for people to integrate together so easy to integrate easy to test and so it's going to be exciting. I'm really excited. I think we have all the ingredients. It's time now to, as I said, make these big problems in small part and start to solve it for helping the next generation of data centers. You've talked about a lot of really cool technology. You've talked about what AlphaWave is delivering in market, and I bet we've piqued the interest really cool technology. You've talked about what AlphaWave is delivering in market,

and I bet we've piqued the interest of our listeners. Where can they engage, learn more about the solutions you're delivering, and engage with your team? Yeah, so definitely start with our website, awavesemi.com. There is a lot of information there in a form of white paper and blog posts. You can also find our YouTube channels where our CTO and our CEO have a lot of information on our technology. And contact us on our website. Our support team would be happy to answer any questions you guys have.

Well, thank you so much for taking some time out of your busy day for this interview. It was a real pleasure. Thank you so much. Thanks for joining the Tech Arena. Subscribe and engage at our website, thetecharena.net. All content is copyright by The Tech Arena.