Semiconductor Insiders - Podcast EP325: How KIOXIA is Revolutionizing NAND FLASH Memory

Episode Date: January 2, 2026

Daniel is joined by Doug Wong, senior member of the technical staff at KIOXIA America, where he has contributed to the advancement of memory technologies since 1993. He began his career with KIOXIA in the company’s Memory Division (then part of Toshiba America) and has since focused on a broad range of memory solutions, including… Read More

Hello, my name is Daniel Nenny, founder of Semaiwiki, the Open Forum for Semiconductor Professionals. Welcome to the Semiconductor Insiders podcast series. My guest today is Doug Wong, senior member of technical staff at Kiyokshia, where he has contributed to the advancement of memory technology since 1993. He has focused on a broad range of memory solutions and has been an active contributor to industry standards. Welcome to the podcast, Doug. Thank you, Daniel. So first question is, what brought you to the memory industry? Well, you know, I've been working for Kyokia.

We used to be called Tushipa Memory Group, but I've been working for Kyokia for 32 years now. And I originally graduated with a bachelor's in electrical engineering from Cal Poly, San Luis Obispo. But in the 93, I decided to, you know, I went back to school and graduated from UCLA. with a master's degree in electrical engineering with a semiconductor physics concentration. So back then, you know, after I graduated, I had to find a job and I happened to find a want ad in the LA Times for a application engineer with Toshiba down in Orange County. So that's what actually brought me to Kiyokshia. Interesting. So as I understand, Kiyokshia invented Nan Flash back in 1987, I think, and then in 2007, they introduced 3D memory to the industry, which is now

widely used in many applications. Can you tell me about 3D memory? Sure. So, you know, back in 1987, you know, we used to be called the Tashiba Memory Division, and we got spun out in like 2018. But, you know, back then, Tachiba invented this technology called NAN flash double E squared prompts. And, you know, we get rid of, you know, we're not calling it E-E-E-Proms much any longer because everyone understands what NANFash stands for. But, you know, prior to, say, 2015, all the NAN flash was planar 2D technology. But it was pretty clear that scaling had kind of hit its limit.

So once it was, it was no longer able to scale any data. anymore, it was necessary to transition to 3D NAND. So, you know, back in 2007, there was a research paper from Toshiba that introduced the concept of 3D NAN flash, even though production didn't actually start until, say, 2015. But this 3D NAN flash is called Bix by Toshiba at the time, and Bix stands for bit column stack. So it's just our trade name for our 3D Nan Flash. Although we still make 2D Nan Flash, 3D Nan Flash now comprises probably 95% of our bit output. So it's certainly displaced the original 2D Nan Flash. Right.

So what features standpoint, you know, what advantages come with VIX Flash? Well, the main clear advantage is we've been able to increase the aerial density, which is the number of bits per square of silicon surface area. And there's a lot of different flavors of 3D nan flash today. So, you know, originally we had, you know, multi-level cell, two-bit per cell technology. But today, 3-bit-per-cell technology, TLC, is certainly the dominant technology with 4-bit-per-cell or QLC technology ramping up, you know,

as people recognize that they want the higher density and lower cost. So this 3D Nan string has enabled us to stack memory cells in the vertical direction. The density can increase significantly. So in the original 2D Nan flash, we were able to achieve a density of around 128 gigabits per die. And it was topping out because like I said, the cell area was getting too small to actually retain the number of electrons that we needed to do in the memory cell. But with this 3D technology, the new Bix technology, we've been able to achieve a terabit in TLC

technology and two terabits per die in QLC. So really this, the main advantage has been the increase in total dye density. And of course, another benefit that's kind of hard to to really appreciate is the fact that the memory cells have reduced the, these bigger memory cells have reduced the intercell interference effects between individual memory cells. And we've been able to enhance the programming speed because of that. So the transition from, for example, MLC to TLC to QLC technology just would not have been possible without the transition to this 3D NAND. And finally, our current generation of Big Flash, which is our Generation 8, we've introduced a new architectural change, which we call CBA, which stands for CMOS directly bonded to array, and that brings even more advantages.

But basically, it's two separate wafers that are bonded together now to create the memory dye. Interesting. Can you talk a little bit more about the CBA technology? Sure, yeah, yeah, that's a great question. First, let me. start out with saying that the NAND industry overall has been using a CUA technology. So that's the CMOS circuitry under the memory array. This was an attempt to make the dyes smaller. So you have the memory array and all the CMOS and logic circuitry was packed underneath that.

And we did do that for one generation, but we've decided to shift away from the CUA technology to this CMOS bonded array technology, you know, with the two wafers. And we do believe the industry eventually will follow on our footsteps. Now with this CBA technology, we've actually separated the 3D memory stack from the actual CMOS logic circuitry. And we fabricate these on two totally separate wafers. And the advantage is we can optimize the temperature processing for each wafer individually. So, you know, with this optimization of processing per wafer, we can get better characteristics.

So specifically, what we talk about is the fact that the memory rate, because it's a multilayer stack of multiple materials, there is a high-temperature annealing step that is necessary to relieve the built-in stress. But the problem is if we fabricated this on a single wafer, then the high-speed logic circuitry would also be subjected to this high temperature step, which is actually detrimental. So by separating and processing these two wafers separately and then bonding them together at the end in a low-temperature step, we can optimize the characteristics for each wafer. So basically the logic wafer never sees the high temperature anneal step that the memory

wafer sees. So basically this allows us to increase the power efficiency, increase the performance, and of course the density is part of the overall equation and it's more cost effective and more sustainable in our opinion. So basically the CBA technology is really the backbone to maintaining. good cap efficiency, at least from our point of view, and that's topic for another discussion. Yeah. So can you talk a little bit about the roadmap for Bix Flash and, you know, what can we expect with the next generations of Kiyokshia's 3D memory? Sure. So, you know, the Bix Flash

that introduced CBA was our Bix Generation 8 product. But this year's future of memory and storage, you know, FMS got rebranded to future of memory and storage. We showed the wafers of our next two generations of products. So this is Bix Generation 9 and Bix Generation 10. So for Bix Generation 9, we introduced a brand new logic wafer, but it's still based on the memory away wafer of Bix Gen 5 and Bix Gen 8. But with this new logic wafer for BigSgen 9, we're supporting the latest JETIC standard. So JEDEC is the Joint Electron Devices Engineering Council, and that's actually where we've been

a big participant in defining the next generation of NANFASH devices. With this new JETIC standard, which is called JESD 230G, for the very first time the NAND interface has been not only improved in terms of performance, meaning the interface speed has bumped up to like 4,800 megatransfers per second, but the NAND interface itself has been changed to support what's called a separate command address protocol. This is actually one of the biggest changes in the NANDSAN. interface since NAND was introduced because historically the command and address and data were multiplexed onto the data bus. So there's like an 8-bit data bus on the NAND historically. And you put in commands or address or data by selecting a couple of pins to select which register the information goes to. But with this new Bix Gen 9 and Bix Gen 10, we're

supporting the brand new separate command address protocol, which JETIC recently ratified. So with this new protocol, commands and addresses are no longer on the data bus at all, and only data follows on the data bus. So we think this is going to, you know, again, support this, the new 4,800 mega transfers per second interface speed. And, you know, help all future NANS as the interface speed continues to increase in the future. So, you know, we're actively involved in defining these new standards at JETIC and will continue to be supporting this effort. Yeah.

How about applications for this technology? You know, AI continues to be a driving force, you know, putting great demands on storage solutions. How does 3D memory help tackle this challenge? Well, we feel that Bix Flash will offer the performance and the efficiency and the density which these new AI workloads will need. In addition, we have specialized variants. So, for example, there's a specialized Big Splash that we call XL Flash, which is basically a low latency NAND. This is also part of the JETIC standard, but it hasn't really. really been adopted yet, but it's basically a low latency nand. There's also a QLC flash,

and QLC flash is addressing the AI market because the AI market is requiring the storage of very large datasets. So we are seeing a lot of demand for very high density SSDs. So, you know, as I mentioned, we have this two-terbit QLC device. And at FMS, we talked about, or we showed a 32 die stack within a single package for a total of 8 terabytes in that package. So this was recently shown. And also at FMS, we showed the usage of that 2 terabit QLC in a very high density SSD from Kyotia. It's a 245 terabyte SSD that we call LC9, and that's supported by our own. SSD division and looking forward so that that's for Bix sign and for Bix 10 we're

introducing a brand new memory array wafer so in Bix 9 we introduced the new logic level you know to support the new Jetic standard but in Bix gen 10 we introduced a new memory array wafer and that's a 332 layer memory array So 9 and 10 really are our next flagship products. So what are some of the other target applications for Bix Flash today and in the future? Well, currently, of course, you know, all eyes are on the AI market and its demands. But, you know, there are a huge number of applications that we are targeting with our 3D nan. So obviously from consumer electronics and cell phones to, you know, smart.

Automotives, we believe that's also coming. Smart homes. Now anything that's really supporting mobility and also, you know, data centers and industrial robotics. So, you know, besides AI, there's a huge number of applications that we see growing. Beyond that, you know, gaming continues to grow. And of course, satellite communications are becoming a new market. So we do see BIC supporting the demands of quite a wide variety of applications beyond its traditional base of, you know, client PCs and, you know, cell phones. Great. Hey, thank you, Doug. Great conversation. And I hope to have you back again.

Hey, great talking with you, Daniel. Thank you very much. That concludes our podcast. Thank you all for listening. and have a great day.