Semiconductor Insiders - Podcast EP352: The Path to High Impact Parallel AI Agents with ChipAgents CEO and Founder William Wang

Episode Date: June 26, 2026

Daniel is joined by William Wang the CEO and Founder of ChipAgents.ai, the category-leading agentic AI platform for advancing agent-based AI approaches for semiconductor workflows. He is also the Mellichamp Endowed Chair Professor of AI and Designs at UC Santa Barbara, and a global leader in fundamental AI research. He founded… Read More

Hello, my name is Daniel Nenny, founder of SemaiWiki, the Open Forum for Semiconductor professionals. Welcome to the Semiconductor Insiders podcast series. My guest today is William Wang, the CEO and founder of Chip Agents AI, the category leading agentic AI platform for advancing agent-based AI approaches for semiconductor workflows. He is also the Mellencamp endow chair professor of AI and designs at UC Santa Barbara, and a global leader in fundamental AI research. He founded the UCSB Center for Responsible Machine Learning,

the Mind and Machine Intelligence Initiative, and the UCSBNLPNLP group. His honors include ICCI SPS Pierre Simon Leplace Award, NSF Career Award, BCS Karen Spark Jones Award, and the DARPA Young Facility Award, and he's on ICCA's AI, tend to watch. Welcome to the podcast, William. Thanks for having me.

So William, as a world leader AI professor at UC Santa Barbara, what takes you to drive agenic AI in the semiconductor industry? You know, what gap did you see that the EDA industry wasn't addressing? That is a great question. So the first time I started building neural language model, it was 2011. It was super early. So at the time, I trained a deep recurrent neural language model to drive the perplexity of language model results to be extremely low. So at that time, people don't believe it, right?

And that was really early. That was before 2012, before ImageNet. And then in 2016, when I became a professor, I came from my PhD at Carnegie Mellon University. And my thesis at the time was actually formal verification. How do you build a statistical machine learning model to do theorem proving and reasoning? So at the time, we were building our first deep reinforcement learning base AI model for reasoning. And it was super early that basically the AI agents is an embedding vector, not as a language model we have today. So we had some early success around 2017.

But in 2024, when we are looking at the space of AI and semiconductor, we realize the technology is ready. We really have amazing opportunities ahead of us to have AI agents to do verification, to do chip design, and being able to really have the real world impact. I think comparing the academia and industry, the biggest difference is that, the impact cycles in the academia is extremely long. So when we first write a paper for video understanding in 2019 for VATACs, published at ICV, the Premium Computer Vision Conference, five years later, Google used my result to run its video understanding components in the Gemini paper in 2024.

So you can see five years later, right, in academia, your research got recognized is published. Whereas at chip agents in the industry, I think the feedback loop is much shorter that immediately, right, we ship our product to our user on weekly basis, the next day people tell you whether it's working or not working. So I really enjoy bringing the fundamental AI technology we developed over the last few decades to an amazing industry

where a lot of innovations is happening and it is the world's most important supply chain. But having AI native solutions to fundamentally change the industry to have AI agents as the new labor to join the labor market, I think will fundamentally change the industry. I agree completely. So how is chip agents fundamentally different from how traditional EDA companies are approaching AI and why does that difference matter? Yeah, fantastic.

I would say that the EDA companies, they are doing great job in building the point tools. So as you can see, that every single layer, right, in semiconductor design manufacturing process, you have a job title, right? You have three different vendors for each layer. And there's all this fascinating tools, right, in verification, in LinkedIn, in CDC, in, you know, simulation, synthesis, you know, design layout. The challenge, right, with the EDA company is that what do I do, right, with the existing point tools?

So a lot of their strategy is basically sprinkling, right, AI features into the existing point tools. So let's say I have a debugging tool, I'm adding an AI assistant, right, to this debugging tool so that you can, you know, ask questions and answer a question. questions for this debugging tool which help you to improve your productivity. It is true, right? It does improve productivity, but our estimate, this is probably around like 10%, 20% improvement. However, Chip agent is taking a fundamentally different approach.

So we're taking an end-to-end approach that basically we are building everything from the ground up, right? We are not starting from a point tool. So we want to build something that allows us to do end-to-end, acceleration from the specification, right, all the way to GDS. So that is our goal, right? Fundamentally, we're building a new platform, allowing us to accelerate the entire, you know, process is not per layer, but is cross different layers

in the design and manufacturing process. All right, so what are the most time-consuming tasks in DV? You know, what specific cycle time reduction are you seeing with chip agents? Yeah, definitely, I would say verification remains as one of the most time-consuming procedure in the design process. And we see that for test plan generation is still taking all these companies weeks of time to generate high quality of test plan from the spec. Formal verification is definitely one of the most time-consuming aspect. So even if you have a very small blog, you want to write a very important.

the task plan for formal very carefully to make sure everything is covered, it's not very easy, right? And then writing a system very long assertion traditionally also take a long time for engineers to go through all of the task cases and then to write assertions. And then you need to basically plug in, right? The theorem pover and they run the whole process, get to a certain coverage, and you have to go from 0% to 100% coverage, include coverage, coverage and functional coverage. So chip agent today for formal verification, we're able to shorten that used to be one to two weeks of time to right now down to less than one hour, right, for some of this block where we autonomously generate the formal task plan and then

the system very long assertion and then allow you to complete the whole loop autonomously with AI agents. So we're seeing great success informal. The same way's functional verification in UVM based solutions. So UVN's architecture is extremely complicated, right? Because the design of UVM was not for AI, was actually for human to reuse, right? The prior library that you use to basically verify the prior projects.

Now, the challenge with UVM is that it's extremely difficult, right, for people to learn UVN. UVM is not being taught at any university, any school. I think probably maybe only, only one or two, right? Schools in the US, they teach UVM. Most of the schools, they just don't teach UVM at all. And then when a new DV candidates,

they go to the job market, they have to learn things from scratch. And because UVM's complexity, it take them a long time, right, to be trained as a DV engineer to do UVM verification. Now with chip agents, we can extend your UVN task bench. We can build on top of it. We can add task cases.

we can add cover groups, cover points, we can help you to build a new UVM test bench. We also see great success in reducing the turnaround time for building UVM test bench by as much as even 400x in terms of the productivity gain. So for formal and functional, I think for chip agents joining the workforce to be able to autonomously render tools, we're seeing great success in the industry for DV. Yeah, I agree with that completely. You know, coverage closure is notoriously iterative. So how does chip agents, multi-agent workflow compress coverage closure? Yeah.

So I would say this is really a benefit, right, from AI agent's solution. So when we first started a company two years ago, at the time, AI is a co-pilot, right? It's assistant at the time. But quickly, you saw that last year that we released the industry's first AI agents for design verification. But then towards the Q4 in 2025, we released the industry's first multi-AI agent solutions for debugging. I think the benefit of having multiple agents doing the work is that many of the tasks in design and design verification are just embarrassingly paralyzed. right meaning that you can basically have five different AI agents to do things in parallel and this will significantly improve the productivity to generate new test cases to go through different parts of the test plan many of the things you can do it in parallel to be able to save the time to find a bug to improve coverage to be able to improve the result so multi-AI agent is definitely a key to

topic for 2026 that we're seeing many of the companies they're moving from single AI agent technology to chip agents, multi-AI agent technology to really accelerate many of the tasks that are paralyzable. Right. So today a tapeout involves hundreds of engineers coordinating across RTL, DV, physical design and sign-off over maybe an 18 to 24-month period. What does the autonomous payout look like in the next decade? Yeah, so definitely I think that we are right now at the cusp, right, to see the industry revolution in AI agents for chip design. I think in the next decade, gradually we're going to see AI agents going from assistance to single agents to multiple agents to even agent organization,

and finally even to virtual chip company. I think all of them will have, happen in the course of the next decade. The key thing I would say is AI agent coordination, right? So if you think about, let's say debugging and bug triaging, right now is human architect, right, calling this meeting where you have designers, devian engineers, all sitting together, and they talk to each other, they read us back, and they find a bug.

But imagining you have these AI agents, right? They coordinate. So my AI agent can actually talk to your AI agent and each expert engineer, you can actually lead a team of 50 to 100 AI agents, and they all communicate with each other and help you debug and help you close to coverage and help you to improve the performance for your digital design. So I think a lot of them will become reality. Key thing is to really build a platform, right, that encourage this generative collaboration

that basically have the agents to work together so that the teams, they can also see the results to really make sure, right, AI agents can adapt and well integrated into the enterprise settings so that they can go from single agents to all the way agent organization and virtual chip company. Yeah, I agree completely.

We're going to see a huge disruption in, I think, verification, due to AI. So final question, William. DAC has been traditionally, you know, where EDA vendors show incremental tool improvements, but this year it feels like different, you know, feels very different because AI is dominating the conversation.

In fact, you guys have the largest booth in the conference. And I was looking at it today, and it looks like you could fit synopsis, cadence, and Siemens booth inside your booth. So, you know, what are the highlights from chip agents? What are we going to see at that 2026? Yeah, absolutely. So I think DAC remains as one of the key conference for EDA, for chip design, for SOC.

At CHIP agents, we definitely value DAC as one of our premium venue that we go every year. So this year, we have a joint presentation with ADI as part of the Tech Talk. where we are going to present how you actually deploy AI agents in enterprise environments and solve practical problem. This is going to be really fun because we're not talking about, okay, doing some, you know, POC or trial evaluation. We're really talking about how do you scale, right, enterprise AI agent deployments inside a chip company, where we are going to share a lot of the successful use cases and also the lesson. learn throughout the process. So I think that's going to be really helpful for our customers to know what exactly to expect when you're scaling AI inside chip design companies. We also have additional

sessions for the exhibit forum where we'll present our results in PPA and timing closure, timing estimation, pipelining. We're also going to share our latest results in multi-Asian root cause analysis as a part of the session. Chip agent, we also have a paper with SC Micro where they're going to share their lesson learned in deploying AI agents in accelerating design verification. So definitely a lot of exciting things that is going on at DAC. And I think in general, this is really good for the industry. If you look at the ecosystem for a very long period of time, that EDA companies have a very, very hard time, right, getting startup funding. So most of the startup, I would say for dispatch, only came to the world in the last few years.

So I think this is really good sign, right, for the ecosystem and in AI for chip design. I think this will fundamentally change the industry, and I cannot be more happy to see chip agents is taking the lead in the pack to be able to really think about the future of AI agents for chip design. Yeah, I agree too. The first time I met you, folks, was at VVCon, another important show. And this was, I think, in 2025. And so over a year, a year and a half, I mean, I am just impressed by the progress you guys have made. So very well done.

You're a pleasure to work with. And thank you for your time. Yeah, thank you very much, Dan. I really appreciate the questions. Hope to see you at that. Definitely. That concludes our podcast. Thank you all for listening and have a great day.