SemiWiki.com - Podcast EP293: 3DIC Progress and What’s Coming at DAC with Dr. John Ferguson and Kevin Rinebold of Siemens EDA

Episode Date: June 20, 2025

Dan is joined by Dr. John Ferguson, Director of Product Management for the Calibre nmDRC and 3DIC related products for Siemens EDA. John has worked extensively in the area of physical design verification. Holding several patents, he is also a frequent author in the physical design and verification domain. Current activities … Read More

Hello, my name is Daniel Nennie, founder of SemiWiki, the open forum for semiconductor professionals. Welcome to the Semiconductor Insiders podcast series. My guest today is Dr. John Ferguson, Director of Product Management for the Calibre Nanometer DRC and 3DIC related products for Siemens EDA. John has worked extensively in the area of physical design verification, holding several patents. He's also a frequent author in the physical design and verification domain. Current activities include efforts to extend physical verification and design kit enablement for 3DIC designs, silicon Botonics, Quantum Compute,

and other HPC architectures. Welcome back to the podcast, John. Thanks, always good to be here, Dan. So John and I have known each other for 30 years, and John, your talent is explaining very complicated things in very simple terms. So I'm looking forward to this discussion. Hopefully I won't let you down.

We also have Kevin Reinbold. He is a 3D IC technologist for Siemens EDA. Welcome, Kevin. Thank you, John. Happy to be here. So let's just get into it. Kevin, how would you describe the current state of 3D IC technology in terms of adoption of the architecture for mainstream

next generation ICs? Yeah, so I think most of the activity that I see is into hyperscalers space, right? It's the big guys doing the big data. Also AI applications, right? I mean, they tend to be the primary consumers of these types of designs at the moment. I think a lot of this data that I'm still using silicon interposers, if we talk in terms of TSMC technology, Coass type technology and similars from the various OSATs,

that tends to be the predominant technology that we're seeing out there right now. But what's exciting right now is that we're starting to see the trend start to expand, where we see some of the hyperscalers, AI needs, needing to scale up beyond what a silicon can provide from a physical standpoint, right? There's reticle limits associated with that. So what we're starting to see are newer technologies or bridge-based technologies. You know, these would be like Intel's eMIB technology, PSMC's CoAS-L technology, as well as, you know, some of the introductions of some of the newer

class interposer technologies. So I see, you know, those are some of the more interesting trends that, at least that I'm seeing, you know, within our customer base. And what are the challenges associated with successful design and manufacture of 3D ICs? I mean, what are you seeing out there? Yeah, Daniel, there's a lot of challenges, right? It is where to start, right? I think the first off is, you know, building a cohesive digital twin of the 3D assembly, something that can serve as a, you know, common source or golden source of truth

that multiple groups can reference. You know, one of the challenges that we see with a lot of our customers is that, you know, you have electronics design focused on building out the connectivity, looking at electrical performance, you know, in parallel, you may have a thermal team that goes off and creates the rotation with that floor plan. So one of the challenges is having a common view, a consistent view of that data, and being able to aggregate that data from a lot of different sources. If you think about it, we're going to have multiple chiplets. There might be bridges as I just referenced a moment ago, there's gonna be packaging information. All of that can come from different sources

and different formats and different tools, right? So you have to have some mechanism that can serve as a data aggregation environment that provides that common view of the floor plan that groups can reference. Beyond that, I think tool capacity, tool scalability, some of the areas are going to be challenging. When we start these 3D IC implementations,

we're seeing pin counts of several million pins for a design. We're seeing bonding technologies like bonding, where we're talking about tens of thousands of connections, scaling up to millions of connections between devices. So not only having capacity to handle that type of thing, but then also the corresponding functionality to help our customers deal with that skill of design in a more efficient manner, things like hierarchy for all.

3D DRC, 3D LDS, how do you, once the design has been completed, how do you verify it's assembled correctly and connected correctly? And then, I guess one of the big concerns everybody has, and I know John's gonna talk more about this, is thermal mechanical performance, right? Understanding the aspects, not only

but the mechanical aspects on electrical performance. Right, so from a technical perspective, tell me about the state of enabling tools and technologies that IC design and verification teams have available to them to overcome, you know, the challenges you mentioned. teams have available to them to overcome, you know, the challenges you mentioned? Yeah, so I think this is, you know, this fits nicely with the introductions that we're making at DAC. You know, last year we introduced a product called Innovator 3D IC that provides for floor planning, you know, for 2.5T 3D IC type assemblies, right? It allows you to figure out how to place these devices efficiently, effectively, and perform predictive modeling for a 2 and 1 3D IC type of design.

When we talk about predictive modeling, we're trying to figure out how do we optimize the design from a power performance area cost perspective. So what we're doing this year is we're introducing building on that and introducing streamlined core workflows really in four key areas. You know, we continue to build on that theme of floor planning and predictive modeling,

also expanding out to provide substrate implementation, you know, being able to take these, you know, EMIB type designs, cell type designs, and physical implementation in an effective manner. We're also introducing new technology to enable protocol compliance, so be able to enable our customers and look at some of the standardized protocols, you know, for die-to-die communications, you know, things like UCIE, for example. Additionally, you know, where we have such an amount of data that come together to formulate these types of

assemblies, we're also introducing work and process data management. So basically a data management solution that allows us to track various versions of files that were formulated to create the assembly and to maintain any of the revision control for that. There's also activity in the multi-physics space. I don't want to steal all of the excitement that John's got to talk about. Great. Thank you, Kevin. So, John, it sounds like successful 3D IC design and verification

extends beyond just a digital realm and into the thermal mechanical area. How common is it for EDA vendors to have multi-physics capabilities necessary to overcome these challenges? Well, I'd say all of the big vendors in this area are working this problem. It's the most important problem. I would say particularly the thermo-mechanical impacts that are coming, the issue that we have is they are ultimately going to change the way that the transistors behave on your dye. that the transistors behave on your die. So if you've got known good die and you're putting them together into a 3D chiplet, just because they were known good die

on the test bench standalone, doesn't mean you're gonna still get the same electrical impact when you've put them in context. So identifying that is critical. We need to be in a place where we're, as we're designing, we're making sure we're getting, progressing in a direction where we're ultimately gonna have more success in the choices that we make

of how we place things, where we place things, and what their ultimate impacts are. Got it. So what advantages does early phase stress analysis using caliber 3D stress offer compared to traditional methods used in the semiconductor industry? Great question.

Yeah, you know, early phase is a key part of this. If you think about a 3D IC, you've got an ability to stack chips on top of each other, side by side. And when you're talking about maybe lots of chips that you're putting together, you've got a near infinite range of possible ways that they can be assembled, but not all of them are gonna be feasible from an electrical standpoint, right? If you make the wrong choices, you get too much heat, you get too much stress,

you're ultimately, your design's not gonna work correctly as you intended it to do so. So you have to start it early. And then as the design progresses, as you start making decisions about, you know, let me look at different ways where I could do the floor planning of the different chips, let's start to then maybe add in information. So instead of just looking at the chip as a block of silicon, we know something about some of the metalizations and some of the oxide data. That will give us more detail to go from. We will need to know something about the power maps as well.

Usually at an early stage, there's not much known, right? You make usually a single power level that you might assign to an entire chip. But again, as you progress further, you start to get more details about that chip. You can run some of the parasitics. You make a more accurate assessment. Those can be added as you go to get you to a point where you're able to make, identify early decisions

where maybe you've made a mistake, right? Maybe I should have flipped which dies on top and which dies on bottom, or maybe I need to separate two horizontally, right? To make sure I've got a bit more avenue for stress compensation and or for thermal compensations. So that part becomes a critical part. To the second part of the question, as I mentioned, everybody's working this.

Everybody's got a little bit of a different slant, particularly, I think, as we'll come to for mechanical stresses. Most of the industry today looks at that from a reliability perspective, where we're really looking at it from a true electrical impacts perspective, as well as ultimately going to the reliability issues as well. Great.

So final question, John. Looking ahead, what future developments or innovations can we expect from Siemens in the realm of 3D IC design and manufacturing? I'd say so far in the industry, we've been in a situation where you can do things like run some power analysis, then you feed that into thermal analysis manually, maybe you do some stress analysis manually. It's a complicated process. Ultimately, this has to all be automated. You've got to be able to go from one operation to the next and then feed back onto the system, right? Because if I change my thermal behavior and that impacts the electrical, that means, for

example, the power that I initially calculated is wrong because it hadn't originally considered that thermal impact. Same for stresses. So we have to build a whole system that does that automatically so that the user's not in the middle of it. That's really where Siemens is going right now. We've got some good efforts in that space

and I expect this time next year we'll be talking more detail about that. Great. And you have a ginormous booth at DAC. So we're at DAC. Hopefully I'm gonna see you guys there. We'll have some coffee. Sounds great.

Looking forward to it, Dan. Sounds good. All right, thank you, Kevin. We'll see you this week. That concludes our podcast. Thank you all for listening and have a great day.