SemiWiki.com - Podcast EP297: An Overview of sureCore’s New Silicon Services with Paul Wells

Episode Date: July 11, 2025

Dan is joined by sureCore CEO Paul Wells. Paul has worked in the semiconductor industry for over 25 years including two years as director of engineering for Pace Networks, where he led a multidisciplinary, 70 strong product development team creating a broadcast quality video & data mini-headend. Before that, he worked for… Read More

Hello, my name is Daniel Nenny, founder of SemiWiki, the open forum for semiconductor professionals. Welcome to the Semiconductor Insiders podcast series. My guest today is Paul Wells, CEO of Surecore. Paul has worked in the semiconductor industry for over 25 years, including director of engineering for PACE Networks, where he led a multidisciplinary 70 strong product development team. Before that, he led a team for Fujitsu MySchool Electronics, supporting ASIC customers in Europe and Israel. Welcome back to the podcast, Paul. Hey, Dan, it's great to be back.

So we're at about the halfway point of 2025. How are things going at Shure Core? Pretty well, actually. You've had a little bit of a slow start to 2025, but ever since then, the business has grown steadily. We've expanded the team. And the good news is we're seeing increased interest in both custom and low voltage memory solutions,

as well as, generally speaking, our low power and low voltage design capability. Yeah, I saw your latest announcement about is generally speaking a low power and low voltage design capability. Yeah, I saw your latest announcement about the launch of Surecore's new suite of silicon services and that sounds really interesting. It was described as a one-stop shop for SOC and IP design. Can you elaborate on how these new services from architecture to test chip evaluation can help customers create power efficient and high performance devices for markets like IoT wearables and of course AI. Yeah well I guess by one stop shot what I mean is we're you know we're capable of working with a customer on anything from a test

chip spec all the way through to an ip block spec and then taking those all the way through to sign off ready gds2 and also liaising with the packaging house of course. So you know we can help the customer with all those aspects. So that's what we mean by one stop shop. We can even actually take it as far as completing silicon level characterisation. So if the customer wants to design part of a production ASIC and prove it before they finally go into production, we can help them set up a test chip, put IP on the chip. When that chip comes back from fab, we can then evaluate across process corners, voltage and temperature. And customers can engage with us at any point in that process. So

we all know the hassle of going from an architecture, an idea for a product all the way to getting into production. And particularly for startups, you know, there are often resource shortfalls in that whole process. So we can help with that because essentially, although we're a memory design company, as I know you know, Dan, you know, we have to have all of those skills in the business and we've been doing it for 10 years now. Yeah, well, given your background in design that makes complete

sense. So Surecore as you said has been known as a memory IP company I'm from the memory world so we know each other quite well. So why are you now offering services? Why is Surecore different to other design services providers? Yeah so that's a really good question because you because there's a lot of pretty competent, capable design service companies out there and are we just another me too type company? And as you said, I've spoken to you many times about this, about the skills that you need for memory design

and to get a compiler completed, you need design capability, you need significant verification focus and characterization rigor, all in order to be able to deliver a complete memory compiler to a customer. So our team are really highly experienced memory and mixed signal designers. They nearly all have mixed signal backgrounds and they've got a deep understanding of transistor level design and layout and particularly, and this is really where we are differentiating ourselves, is really the impact of low voltage operation and the way it exacerbates process variability and design marginality. So those additional

skills really enable the team to identify and resolve both design and layout issues rapidly and effectively. Also, because of the regular structure of SRAM, then it really mandates that you move towards a highly automated design flow. So consequently, the team are exceptionally good at building automated flows, whether that be verification, whether it be layout in certain cases.

So those automation skills coupled with our experience really allow us to deliver high quality design and layout faster than most teams we've engaged with actually. Yeah, you know, we're also seeing a rush to the advanced nodes, which poses additional challenges, you know, like leakage and thermal management. How does your core's expertise in low power design enable customers to overcome these types of hurdles and deliver sustainable next generation silicon? Yeah, well, unsurprisingly, we're seeing demand for specific applications, particularly in the things like hearing aids,

smartwatches, and increasingly Edge AI as well. Well, all of these need a big emphasis on power management. So Edge AI in particular has to take care of dynamic power and also not just for power consumption reasons either. Some of these newer ambient computing products, there was something called the Humane AI pin, for example, that was known to get pretty hot in use. And again, that would just be because of this sheer amount of computation that was taking place in a very small factor device without, of course,

no kind of forced cooling in handheld or all these new small ambient devices. So also it's been known to affect various brands of smartwatch. So when you're executing GPS tracking and we've got the weather like we have in the UK today at 28 degrees, then these devices can get quite hot, which of course has knock-on effects for long-term reliability. So really this is where our expertise in both reducing

dynamic power and operating voltages, which of course is a big help in reducing leakage. And not only that, also affects transistor behavior and design marginality, which we understand thoroughly from the world of memory. That means we're really ideally placed to work with our customers to help them deliver power optimized silicon IP solutions. Yeah, yeah, it's interesting. You know, as you said, analog mix signal design service focus, your design service focuses on low power solutions for applications like Edge AI and medical devices. Could you talk a little more about that?

Can you share how SureCore's experience with low voltage design helps ensure energy efficiency while also meeting the rigorous demands of these markets? Yeah, I guess there's two projects that we did, both Reg.AI companies actually, and the example I'm going to give you is for a couple of memories. One of them was operating at interfacing at 0.45 volts while the core operated at 0.65 volts. In the other case, the memory was designed to operate to a nominal voltage of 0.6 volts. So obviously with the minus 10% characterization point taking it down to around about 0.54 volts. So really we had to, you know, extensive design care was needed for both of those

designs and a lot of these kind of products are starting to take advantage of what I would call them mature FinVet nodes, like 16 nanometers and 12 nanometers. So they both offer excellent digital and analog performance whilst being very cost-conscious, you know, or cost-competitive, should I say, not cost-conscious. So the considerations we needed in low-voltage design, like reduced headroom and increased process variability, again, from the world of S-ROM, it means our team are really well placed to be able to engineer very power efficient designs for these kinds of applications.

Right. Well, as you said, SureCore's full custom transistor level layout services tailored for high performance area efficient designs. But how does your team focus on precise device matching and shielding given customers a competitive edge in the power and performance area? So again, again, I'd say this really comes down to expertise and experience and you know I've seen typically have an excess of over 30 years experience So, you know, they know all the tricks they need

They know what's needed to ensure both an area efficient layout as well as one that's configured to address matching, shielding, and not just those two things, but also really good quality power distribution. You know, we're talking about designs which can have very high dynamic power consumption, particularly with these edge AI designs. So getting good power grids is very, very important. So you can both minimize IR drops and also electron migration effects.

Right. So I read that the mixed signal verification and characterization service that you provide uses advanced techniques like statistical analysis across process, voltage and temperature extremes. How do those methods combined with automated library file generation ensure robust designs and faster integration for clients aiming for rapid market entry? Yeah I mean

again we're leaning on our expertise from the memory space and delivering memory compilers in a reasonable timeframe with a small team mandates really efficient and effective design flow automation and statistical analysis. So we apply those skills when we're developing mixed signal blocks as well to build comprehensive test benches. We have automated waveform analysis features that help accelerate the characterization and the verification process. As you know, we've been a power user of Solido now for probably around eight years and we're very adept at assessing design marginality and getting the best out of that tool. So we can also rapidly set up characterization environments that can extract key digital timing across PVT corners, and again,

automatically generate these all important lib files. So those.lib files, again, they're quite often overlooked in the mixed signal world, but they're really essential if people are gonna be able to quickly integrate a key analog IP block index in a digital circuit. So when you mentioned test chip development, so you're talking about the entire test chip development

and evaluation services, which supports silicon prototyping, right? For analog IP blocks like converters, PLLs, LDOs and band gaps. Can you explain a little further how SureCore's end-to-end support from architecture to post-silicon evaluation, how you guys do it, how does it reduce risks and accelerates time to market for the new innovative

designs? Yeah, I mean it's quite interesting actually. We're actually doing this for a key customer of ours at the moment and hopefully we're going to be able to do a press release with the customer about it in September. So we're exploiting our test chip design and evaluation skills and we've also created a small lab in our office in order to provide a service that's often very difficult to find on the open market, actually. So not only can we design an architect, the test chip, for customers, we can then develop the custom hardware, which allows that test chip to be thoroughly characterized

in the underlap conditions. And that could be multiple IP blocks, which we can then test across process corners, if the customer has those from the say the MPW run as well as voltage and the standard temperature range minus 40 to 125, we have that capability. So, you know, we're skilled with such things as LabVIEW and we have a whole bunch of test equipment that we've assembled over the years

and we can rapidly create the test code, which is needed to characterize a wide variety of both digital and analog test blocks. So I'm kind of hoping this is gonna become quite a popular service, you know, especially for silicon startups. There seems to be quite a bit of an uptick in the startup space at the moment.

And, you know, we all know the challenge of getting a chip out the door and really the kind of the lab hardware skill set that's, I wouldn't say it's forgotten, but it's often not part of the core skill set in a silicon startup. So we can really kind of come to the rescue there if you like, and provide our capabilities. And that's really important because, you know know we can help accelerate the all-important validation of a test chip and that can be critical in order for a company to make the correct decisions, design decisions for the production ship. So I think it's a really important service and again we have the skills to be able to do that. Great. So, final question, Paul. What's next for SureCore? What will be your key focus for the rest of the year? Well, you know, having launched these services,

the goal is to build our customer base. We want to talk to as many different customers as possible. And on the back of that, grow the team further. You know, our customers who we're working with already tell us, they regard us as a safe pair of hands. And as you know, Dan, with the push to get chips out the door and faster time scales on more advanced nodes, the pressure on teams is just getting more and more intense.

And, you know, we're a trusted company who people can come to for any of these skills and we'll help get them to market as quickly as we can. Yeah, you know, as we've all learned, trust is important in the semiconductor industry. And I think, you know, this is probably the most exciting time in the industry in my career. Yes, absolutely. Yeah, there's a lot going on. Thank you, Paul. Great conversation. And, you know, let's touch bases again towards the end of the year and get an update. Yeah, great. Great to talk to you again, Dan. And yeah, hopefully, hopefully I'll get a chance to visit you in California at some point in the near future. That concludes our podcast. Thank you all for listening and have a great day.