SemiWiki.com - Podcast EP309: The State of RISC-V and the Upcoming RISC-V Summit with Andrea Gallo

Episode Date: October 3, 2025

Daniel is joined by Andrea Gallo, CEO of RISC-V International. Before joining RISC-V he worked in leadership roles at Linaro for over a decade and before Linaro he was a fellow at STMicroelectronics. Dan explores the current state of the RISC-V movement with Andrea, who describes the focus and history of this evolving standard.… Read More

Hello, my name is Daniel Nenny, founder of Semiwiki, the Open Forum for Semiconductor professionals. Welcome to the Semiconductor Insiders podcast series. My guest today is Andrea Gallo, CEO of Risk 5 International. Before joining Risk 5, he worked in leadership roles at Lanaro for over a decade, and before Lenaro, he was a fellow at SD Microelectronics. Welcome back to the podcast, Andrea. Thank you. Thank you for having me. Can you first talk to us a little about RIS 5 and what makes it special? RIS 5 is an industry standard. That's the most important thing.

Think of RIS 5 just like the USB or the Wi-Fi. I worked a lot with USB in the past and on the standard. So an industry standard is a publicly available specification that you download publicly, publicly freely and wherever you are in the world be it Silicon Valley or Europe or India or the Far East you can do your design and your implementation locally where you are and compliant to the global standard and risk five is the same what makes it so successful is that the specification as I said are available under the Creative Commons there's no licensing fees and this has grown exponentially from UC Berkeley to being used in very successful products and

companies like Nvidia for example. And these, we have seen this great momentum from so many companies that are engaging and contributing to shaping the evolution of Brisbane. And the other great value that makes Fris 5 unique is that the architecture itself, the ISA, there's a core base ISA that is extremely small and efficient and then there are many extensions standard extensions that you can use depending on your design and you can customize your product based on your workload this is what we refer to as workload optimized silicon or workload driven silicon and risk five enables this and risk five has been designed for vector processing and now we're adding metric processing it supports all these data formats for

a iML so risk five and there is five i say has been a i native since since the beginning so there are many many many reasons why it's it's so special and there's such excitement and vibe and speed of innovation around it yeah usp is a good analogy you know we see momentum behind risk five growing all the time. It's a very popular topic on semi-wiki. What are the highlights you've been seeing over the last year? I would take the RIS 5 Summit North America from one year ago as a starting point. At that time, we announced the availability of the RVA-23 profile specification. That was a cornerstone. That profile specification, a mundane, a set of RIS5 extensions for a more than high-performing application processor.

It provides and it enables binary compatibility at the application level. What it really brings is the fact that operating system vendors can target the RVA 23 profile specification, can build their operating system and Linux distributions for the RVA 23 target. They build it once and it will run on all the RVA 23. 23 compliant implementations. So this is enabling consistent adoption of the R-V-5 application processor profile. This enabled, for example, the announcement by NVIDIA last July at the RIS-5 summit in China, where they disclosed that they're porting CUDA to RIS 5, and they are doing it now thanks to the RVA

be profiled because it removes any unnecessary fragmentation. It allows all the software vendors to focus on one stable baseline. And, well, Nvidia one year ago disclosed as well that just in 2024, probably they shipped one billion risk five cores in all their GPUs. So that's one key message from last year that got confirmed a few months ago by NVIDIA targeting RVA 23 for good aborting. The other major event is Infinion announcing that the automotive microcontroller roadmap is all based on RIS 5. That was done at Embedded World in March 2025.

And since then we have seen growing momentum of automotive on VICE 5 and especially in the automotive special interest group and we also had risk five automotive conference at the iA mobility event a couple of weeks ago in Munich there's so much going on in the other areas in the other verticals data center automotive we got requests to start a special interest group about risk five in space which is somewhat adjacent to automotive but has its specificities so this concept of the special interest groups is very valuable. It's where we bring together the domain experts from automotive, from space, who may be new to RIS 5, with the experts from RIS 5. How would you run Autosar on RIS 5 ECU? Which RIS 5 extensions? We will provide the answers. The other event is from last week.

Google donated a significant amount of credits for Gemini to projects that would use Gemini and AI to accelerate porting of software to RIS-5. The candidacy is open. The call for contributions and proposals is open, and we will announce all the projects that are receiving these credits at the RIS V summit in just a few weeks. Yeah, right. Wow, that's exciting. Yeah, the RIS V summit is October 22nd and 23rd at the Santa Clara Convention Center, one of my favorite locations. So I will definitely see you there. What are you most excited to share with the community at this year's summit? We have aligned an exciting list of keynotes and speakers that will make attending the summit really valuable. We will have NASA speaking about RIS 5 in space from the NASA perspective. Google will provide a keynote about porting software to RIS 5 and how they ported the cloud stack to RIS 5. We will have the Ethereum Foundation explore and describe how RIS 5 can be used in blockchain,

how RIS5 can be used as the official intermediate ISA for blockchain. our chief architect and original founder of RIS5, Chris Zazanovich, which will provide the usual state of the union, which is one of the most attended talks at summit. So there's a lot, there's a lot. And not only the keynote speakers, we will have also analysts like the SHD group that will report on how, from their analysis, RIS V is exceeding expectations. And I can tell you I'm eager to attend that talk. We will also have panels from the Linux distra vendors and the panel on automotive from key industry leaders who will describe the progress of support of Linux on RIS 5 and the adoption of RIS 5 in automotive. So overall you see the message is RIS 5 is everywhere.

We see traction in data center, HBC, automotive, AI, embedded space. there's so much and you will be able to listen to all the industry leaders and keynote speakers and you will be able to network with peers. You will understand that risk five is ready for your application. And the other thing is that we will also, for the first time, have a developer workshop. Right. Can you tell us a little bit more about that? You know, can you explain what that is? We got feedback from the past events from some of the developers. They were telling us, RIS 5 is exciting. Your conference shall be as exciting as RIS 5 is. Your summit shall be engaging, shall be fun, shall be interactive. And that was a comment feedback that we took really serious.

So the developer workshop is one day, the first day of the event, event in a special area with a very low-cost entry ticket for the developers. And we will have two tracks, one on software, one on hardware. These tracks will not be brain dump. These tracks will be lectures from experts and hands-on labs. That's the key part. We will have Google, AWS, Red Hat, Sci-Fi, Zemans, Deep Computing, Restart Solutions, Harvey, Matt College, Blue Speck, Chip Inventor, App B technology, all these companies will provide lectures and hands-on labs.

For example, one, I cannot disclose too much. I cannot help the developers upfront, but one of the labs will be in there will be a risk five core publicly available core in system very log that raises an exception and during the lab the developers will have to find out if it is a software problem over our system very low problem and fix it. So hands-on inside a RIS 5 core. There will be labs about porting AI and running LLM on RIS 5, or optimizing full vectors, or building YOcto. To be honest, I'm quite envious.

I would like to be back to a junior developer and be part of the workshop. That's where the engineer or the geeky, nerdy side out. Yeah, that sounds good. I'm looking forward to it. The software ecosystem support is key to the success of Risk 5. Can you talk about the status of software enablement on Risk 5 and how you'll be addressing

it at the summit? Yeah, sure. We are working extremely closely with the Rice project. We are working as close as possible together as one. We are working together and Rice, the Rice project is driving, porting, and we are working porting optimizations of languages, tools, libraries, frameworks to respite. I see this critical as enablement optimization. I see these even more critical when we start addressing together complex workloads.

That will help us identify opportunities for further innovation. Together with Bryce, a few months ago we announced that we upgraded our membership in the Yachta project, project to the platinum level. Together, RIS V International and the Rice project. This is a bold statement. Being at the platinum level enables RIS5 to be on par with the other ISAs. The YOcto project is already building and testing for RIS 5 on their builders. And the goal is that RIS 5 will land in the official CI, and will be supported. So having an embedded Linux distribution that is well tested, well maintained with an LTS, with all the tools to optimize it for your embedded device, is critical to the

embedded developers, it's critical to Edge, IOT, intelligent Edge. And it has this incredible value of the baseline for focusing on upstreaming, focusing on upstream well-tested kernel support. So this enables the entire software ecosystem. And this leverages the RV823 that I was mentioning before. The Linux, the commercial Linux distributions are getting ready to support RIS 5 officially. And I was mentioning Nvidia before. So I don't want to repeat myself too much. But these are all the actions that we are driving. And final question, where do you see Risk 5 in 10, 20, maybe 50 years from now?

That's a hard one. I love the numbers that I'm getting from the analysts. You know, as Risk 5 international, we do not collect royalties. So we don't have official numbers ourselves. We rely on the numbers disclosed by our members, like the 1 billion cores shipped by Nvidia alone in 2024. We rely on the numbers coming from the analyst, the SHD group in their 2025 report. They predict that in six years by 2031, RIS 5 will be shipping 20 billion, will be shipping in 20 billion stocks in 2013 and every sock has multiple RIS 5 course. So I like those numbers. I, in the future, I really see RIS 5 as, as the architecture for the future of computing, the default choice for every new design.

So I would say, come to the summit and find out how we're making this happen. That's great. I agree, by the way. So thank you for your time. Great to talk to you again. My pleasure being with you again. I will see you in Santa Clara in just a few weeks.

Thank you. That concludes our podcast. Thank you all for listening. and have a great day.