SemiWiki.com - Podcast EP322: A Wide-Ranging and Colorful Conversation with Mahesh Tirupattur

Episode Date: December 12, 2025

Daniel is joined by Mahesh Tirupattur, chief executive officer at Analog Bits. Mahesh leads strategic planning to develop and implement Analog Bits’ vision and mission of enabling the silicon digital world with interfacing IP to the analog world. Additionally, Mahesh oversees all aspects of Analog Bits’ operations to ensure… Read More

Hello, my name is Daniel Nenny, founder of semi-wiki, the open forum for semiconductor professionals. Welcome to the Semiconductor Insiders podcast series. My guest today is Mahesh Terrapatour, Chief Executive Officer at Analog Bits. Mahesh leads strategic planning to develop and implement analog bits vision and mission of enabling the Silicon Digital World with interfacing. to the analog world. Additionally, Mahesh oversees all aspects of analog bits operations to ensure efficiency, effectiveness, and financial security while maintaining strong relationships with key stakeholders, customers, and employees.

Welcome back to the podcast, Mahesh. Thanks, Dan. Good to see you. So, Mahesh, you've been with analog bits for over 20 years. Analog bits has a broad portfolio of customizable IP. I mean, what an impressive journey you've had. You know, can tell us a little bit more about your. journey? Yeah, joined Analog Bits in 2003 between my two sons. I almost called this company

my middle child. It's been a, so that's why I'm always in love with this company. It's been a, it's been a wonderful ride. The company was started buying an amazing engineer, Alan Rogers, and then I joined him in the journey and we both built a company. We really focused on building great engineering products and mixed signal IP. IPs is our specialty. We started in the clocking area, and then we moved into the sensor IOS and SIRD's area. And then we started seeing more and more demand for sensors.

So we broaden the sensor portfolio. And as we're also doing the sensor portfolio, customers started saying, well, now that you've sensed, how do I fix it? So we started coming up with IPs to enable better power management, both measurable, observable, and safer delivery of power. Along our journey, TSM has been one of our key partner, though we worked with other foundries such as Samsung and Intel and Global Foundries, but TSM has been one of our key

partner and has enabled the growth and success of this company. It's been a very symbiotic partnership. We've been TSMC OIP partner since 2004, so that almost takes the time that I joined the company. In fact, that was my first mission is to get Analog Bits into PSMC OIP program. And that's given us a lot of visibility and credibility to demonstrate our IPs to customers. Yeah, you know, you and I have been friends for many years. And, you know, I followed your journey, you know, with you on semi-wiki. And I see you at just about every event.

I mean, we see each other quite a bit. And but, you know, 2025 seemed like it was a very busy year for Analysi. Bits, Mahesh. You know, let's explore some of the highlights of 2025. You know, I saw you at both the TSM Symposium and the CSMC OIP award luncheon. So you've got some awards. Can you talk a little bit about that? Yeah, the OIP award is a very strong endorsement by TSMC and offers this huge credibility. 2025, we were extremely busy. We had got several versions of our three nanometer silicon that we were bringing up in the lab.

We had advanced customer engagement, and then we had taped out our two nanometer, middle of last year, towards end of 2024, and the silicon was coming back for that as well. So there was a lot of excitement and a lot of activity there. We broaden the portfolio of IP. We really increased the portfolio in terms of helping customers manage power and deliver safe,

power to their chips. And this has been a problem. It's been talked about, but not many IP companies stepped into solve it, and we were the first ones to embark on the journey. So besides the thermal and the performance issues that people face, dealing with power supply regulations becoming more and more enough issue. So 2025 was a lot of activity in that area. So we were honored to receive the OIP analog partner of the year award. We were also very happy to have had presented five joint OIP papers. Every vendor presents OIP paper, but doing it jointly with five different customers is quite a feat. It was almost a dream and then everything came true. So we presented a paper with ARM in terms of them using our power management LDOs.

for managing power for their multi-core CPU designs. Cerebris, how they're managing the largest silicon wave for chip in the world with our power supply sensors. With NXP, we talked about our automotive grade suri's and how they've had very reliable low-power surdees and high on the automotive silicon. And social next talked about our pinless technology in terms of how they used it in data.

data center and another company in China called semi-drive that also talked about our automotive great studies. So yes, that a lot of activity, we are a small company, but we had a lot of action in 2025. Yeah, it was a great year for the industry, certainly, and for IP companies and analog that seems to have really enjoyed a lot of success. You know, Mesh, I heard you talk about to the intelligent power architecture. Can you explain what that is? Yeah, we offer a diverse set of IPs, the clocking, thermal performance,

and critically working with DSMC with some of the most advanced customers, we have heard and we found out that managing energy efficiency in AI, especially in the next generation systems where the performance is scaling pretty high, it's really you've got to optimize on multiple facets, the system silicon packaging, and it's all leading towards rack power density.

So managing power is becoming a very, very important aspect of every SOC, both in the data center side and the AIML side. And there are sort of two categories of SOCs, one that is called heterogeneous, where everything is running at full speed and then homogeneous, where everything is also running at full speed, but they run it, it's either full throttle and homogeneous or heterogeneous is running at different speed points. So customers want to optimize power and energy in each of those systems. So we have a vast set of differentiated IPs to help customers track power. For example, and the power supply is bouncing, we can tell them exactly when.

the power is going high, the voltage is spiking, and they can throttle the clock frequency instantaneously. And if the power supply is dipping, they can immediately take corrective actions, either boosting through an LDO externally or on die. So offering these intelligent IPs makes customers life a lot more easier to make their power trackable, observable,

measurable, and measurable. And that's a very key. advantage for future customers. And especially in advanced process nodes, these IPs never existed. Many of these lie as external components, either as external LDOs or PIC chips, which are external to the dye, but with the whole integration of chiplet and everyone wants to bring everything on dye, these analog functions, which are all externally resident, are all getting internally embedded. really where we are focused on building these very intelligent IPs that can be embedded on silicon and at the same time it's area and power efficient.

Great explanation, Amesh. Can you also talk a little bit more about pinless IP? You mentioned that and I don't think we're all familiar with that. Yeah, most of these analog IP designs today, if you look at it, whether it's a PLL or a sensor, they usually require a dedicated analog supply going into the power these analog macros because there are many analog components which requires a cleaner power source going in but customers today are embedding these not in fives and tens but in tens and hundreds so if you were to put about a hundred macros of these sensors and plls you can't have 200 bumps going in it's just ridiculous so yeah you you can share some of them but still it becomes a routing headache and customers are already

facing issues in terms of routing their power to their core logic so to burden them with also having to power the analog macros with these bumps is a nuisance factor so what did happen in the fin-fed node was the supply voltages started scaling down and the delta between the i.o and the core voltage started becoming smaller, what that means is we could now start building tiny pumps and LDOs. I think of them as little like mini transformers. Instead of having to bring in, you know, 220 walls into your home, you can just take a 110 and throttle it up where it's needed and then for your washing machine or for your car and then everything else can be on 110 walls. So the similar concept we use for building these analog IPs, so what this allows customers

to do is they don't need to worry about bringing these analog voltages anymore into these analog components. They just powered off standard core digital. We pump the voltage, filter the voltage, and we provide a clean source at the point of use. So this way they have the full freedom of placing these IPs anywhere on the die like a digital nan gate. It also reduces bill of materials because now you don't need any external components. So a lot of the automotive customers find this enormously helpful and so as the data center customers because now they've reduce the external exposure with all the ESD and the filter caps and they can integrate them anywhere and everywhere on the dye. So really simplifying the life for all the ESD for all the ESD

for all of the analog to integrate analog components on these modern digital chips. And if you look at all the gate around processes, they're all core voltage only. So which means there's no analog voltage at all. So if you need to generate your own analog, you need to have it locally generated in your own circuit techniques.

So that's kind of the underpinnings of how we started the pinless technology. And now that we seem to be gaining more market share for sensors and PLLs and other IPs as well. Wow, that's great. Mahesh, it seems that power sensors on advanced nodes will help with AI deployment. I've heard the AI guys talk about it. Can you tell us a little bit about that from your perspective?

Yeah, absolutely. If you look at the AI customers, their chips draw in thousands of amps. You know, when you and I were designing, we were having tens of amps and we thought there was a nightmare. Then it went to hundreds, but now you're talking thousands of amps. So there is a large amount of power density in a small given surface area. And when these power is fed into these chips, they are not a continuous power. They're very, very surgy. It goes up and down.

And when these go up and down, the logic obviously gets throttled with these power supply variation, and what that impacts is the performance of the chip. And usually the S-RAMs are in a separate rail. So the S-RAMs don't throttle that much, and the logic goes up and down. So there is a huge difference in power delta between whether the memory is being fed and what the logic is being fed, and therefore the clocks have to throttle itself after sensing when there is an extreme high-power event. So where we are working on is we can provide customers warning.

when the power supply is going to spike or has spiked and take instantaneous corrective action. The instantaneous corrective action could be lower the supply so that you can eliminate these extreme high spikes or lower the speed of the clock or load balance the chip by moving the fast-performing blocks across to another domain. So we give them all the metrics to take instantaneous corrective action. So these sensors have to be very fast and have to be doing it in real time.

Cerebrus presented a very nice paper how they're able to manage power instantaneously when these macros are spiking and the power supply is spiking quite effectively. So these sensors are becoming more and more important. They become like instant security alerts for customers in terms of if any events are going on, they can take corrective action immediately. Right, that's actually why I asked. I read this Cerebus paper. In fact, I'm writing about it.

It was very impressive. Listen, Mahesh, last question. Analog Bits is known for giving out custom wine during the holidays. And you always give me a bottle, and I really enjoy it. But I heard you made a comparison of why wine is like analog. That's an interesting comparison, Mahesh. Wine is an analog sensation, then.

Though it's a binary outcome whether you like it or not, but the nuance of the whole analog experience is tasted in wine. Yeah, I mean, being an analog engineer, I also got quite a bit into studying wine and, you know, educating myself a little in wine. Every year, we've been giving out a good Napa Valley wine with its Cabernet Sauvignon or a Cabernet-Fronk. But the wine, the process of making wine, especially in some of the newer varieties like the Bordeaux, is you blend the wine with multiple grapes. And analog design is also a blending technique. So you blend different components of digital and analog, and you come up with a macro, which works in a digital environment. So I had a nice presentation at Silicon Catalyst this year. If you are a wine sponsor, they don't want you to talk about your products, they want you to talk about something interesting and exciting.

So I made a parallel comparison of analog engineer to a winemaker, how one is a physicist and an engineer at heart, and the other is a blend master and a chemist and a biologist in his heart. And both of them come from the same cut of the DNA, striving for perfection and continuous improvement. So I kind of find the winemaker and an analog engineer to be quite interesting characters and the outcomes are quite similar except one comes out as a bottle of beautiful wine and one comes up as a piece of an amazing IP. Yeah, I was at the Silicon Catalyst event.

I mean, that was the best presentation of the day. Hey, Mahash, great conversation again. Thank you for your many years of friendship and the great analog IP. And of course, thank you for the wine. Thank you. My pleasure. And thanks for including us in all your great podcasts and all the coverages that you give us. Thanks, Dan. That concludes our podcast. Thank you all for listening and have a great day.