SemiWiki.com - Podcast EP351: A Detailed Overview of the Emerging Standards for 400G with Kent Lusted

Episode Date: June 19, 2026

Daniel is joined by Kent Lusted, a Distinguished Architect at Synopsys and an integral part of the company’s Ethernet IP design team. He has been an active contributor and member of the IEEE 802.3 Ethernet PHY standards development leadership team for more than 15 years. Prior to Synopsys, Kent worked at Intel for 30+ years, focused… Read More

Hello, my name is Daniel Nenny, founder of Semaywiki, the Open Forum for Semiconductor professionals. Welcome to the Semiconductor Insiders podcast series. My guest today is Kent Lestead, a distinguished architect at Synopsis and an integral part of the company's Ethernet IP design team. He's been an active contributor and member of the IEE-E802.2.3 Ethernet 5 Standards Development Leadership team for more than 15 years. Prior to Synopsis, Kent worked at Intel for 30-plus years, focused on the I-TRIPELE

focused on designing Ethernet board products and performing Ethernet interop debug all over the world. Kent is currently the electrical track chair for the ICCI P802.303 DJ Task Force and chair of the IAE802.8402Gibbut signaling study group. Welcome to the podcast, Kent. Thank you very much, Daniel, for having me. I guess this is our second podcast, Kent. We did one while you're at Intel. So can I ask, what brought you to synopsis? I joined Synopsis in January of 2025 after spending more than 31 years at Intel, as you noted. A big part of my career there was focused on Ethernet networking, primarily developing and deploying NIC cards.

But for the last decade, I was heavily involved in IEE802.3 standards work. And when Synopsis reached out with an operational. opportunity to join their interface IP team, I felt like it was a great fit with a meaningful impact. The synopsis role gives me a chance to stay close to the Ethermet standards, but also have a broader impact across more products and more of the industry than I could from the perspective of my previous company. Great. So why is the industry pushing? towards 448G surdays now and what system level drivers are making this transition urgent? Great question. The responses I'll provide here, of course, serve my personal opinions. The push

towards 400 gigabit per second per lane surtees is being driven first and foremost by the way, artificial intelligence, AI and high performance computing, HPC, systems. systems are evolving. In prior network generations, much of the focus was on the classic front-end data center traffic, which consisted of server-to-switch and storage and general purpose cloud connectivity. Now today what we're seeing is the center of gravity shifting towards AI scale up and scale-out fabrics where the dominant requirement is moving very large amounts of data quickly between different accelerators.

And in these types of systems, GPU to GPU and XPU to XPU communication is no longer a secondary concern. It's the primary determinant of application performance, model efficiency, and overall cluster utilization. Now let me give you three factors. One major driver is bandwidth density. Now, as accelerators become more powerful, each device must exchange more data with its peers, memory resources and switching elements.

And if the IEO bandwidth per device does not scale fast enough, the systems become communication limited rather than compute limited. And that means that the accelerators like GPUs or XPUs sit idle waiting for data. Moving to 400 G per lane signaling is therefore about preserving system efficiency by increasing the bandwidth per lane and enabling higher aggregate throughput within a practical package board system footprint. Now the second driver is Radix. And in these AI clusters, the rate. Ratings matters because it determines how many endpoints or links can be connected within domain, whether domain is a single tray, a rack, or an entire cluster.

And higher effective bandwidth per lane can support higher radix systems, flatter topologies, and fewer intermediating stages. And those characteristics are attractive because it can reduce contention, lower latency, and simplify the network architecture. In practical terms, better radics and bandwidth density helps designers build system that look and feel more like tightly coupled compute fabrics rather than the traditional hierarchical networks and front-end data networks. Now, latency is also a.

critical factor. Many AI workloads, particularly in tightly synchronized training and inference flows, are highly sensitive to communication delay and jitter. As cluster scale, operators cannot rely only on adding more links. They also need faster links. At the same time, they must manage power, thermal density, serviceability, reliability, and that's what makes 400 G per lane so urgent is that the industry is not just chasing a bigger number. It's trying to solve a multivariable, highly complex system problem involving performance, power, cost, reliability, time to deployment. And another important reason the transition feels urgent now is that the industry is approaching

the practical limits of what conventional electrical reach can do at these rates. As the signaling frequencies rise, the loss, the reflections, cross talk, packaging constraints, and connected formats, all of these different aspects become much harder to manage. The challenges are pushing system designers towards a broader co-designed model. And that co-designed model means looking holistically at the search the package, the traces, the Ford, the connector, the cable, and all the little pieces, as well as the increasingly important optical interconnect. In other words, for energy plane is simply not the next electrical rate.

It's part of a larger architectural shift in which electrical and optical technologies need to work together closely to deliver the required reach and density. So the short answer is this. The move to 400 G per lane is being pulled by AI system architecture, not by networking alone. And there's a need for more accelerator bandwidth, better ratings, lower latency, and higher density and interconnects. It's forcing the ecosystem to act now. And the result is a transition from a world centered on conventional front-end networking to one increasingly focused and shaped. on AI scale up and scale out fabrics where the interconnect performance directly influences the

usefulness of the compute itself. Okay, great. So where does the standards effort stand today for 400G Ethernet? I mean, what is the process and timeline? Yes. The standards effort for 400 gig per lane Ethernet is at a very early but very important stage. The IEE802.3 400 gigabit per second per lane signaling study group was initiated in March of 2026 to develop the project documentation for this next rate of Ethernet. In practical terms, that means that the industry has formally recognized the need for the effort, But it's still in the phase of defining the project scope, technical objectives, and the overall framework that a future task force would use to create a detailed specification. Now, let me explain because there's some subtle details here.

This distinction between the study group and a task course is important. The study group is not yet riding the full technical standard. The study group is answering the foundational questions of what is the problem the project is solving? What interfaces and reaches should be covered? And what objectives are realistic and broadly supported by the ecosystem? Once that work is completed and approved, the project can transition to a task force. A task force is where the deep technical work is done, baseline proposals are selected, draft Texas developed, technical tradeoffs are debated and resolved,

and the specification progresses through ballot cycles. So from a timeline perspective, this effort is just beginning. And the near-term focus of the study group is on completing the project documents and rallying the community around a clear set of objectives and goals. If that progresses smoothly, and I expect it well, a reasonable expectation is the project could transition to a task force in late 2026. Now, after that, the normal ICCLE development cycle continues, which is the baseline, the baseline selection, draft development, multiple rounds of technical review. The key point is that industry is now at the quote framing the problem end quote stage and is not yet at the quote standard in progress or standard nearly done stage. So the bottom line takeaway here is that the process has started. The work is real and ongoing and the standards community is building the foundation for the next generation of Ethernet.

But this is still the early phase. The study group, again, is focused on establishing the technical and procedural contract for the work ahead. And if that continues on the current path, the overall project extends into the latter part of this decade. Wow, that's an aggressive timeline. So what are the biggest technical challenges the industry needs to solve before the 448G class implementations can scale broadly. Daniel, there are several major technical challenges that industry still needs to solve before 400 G per lane implementations can broadly scale. Now, the first of that is that the current 200G per lane generation still needs to be fully completed and deployed in industry.

The IEEP 802.3 DG task force that's working on 200G pro lane signaling is establishing many of the electrical, optical, logic, and architectural building blocks that I expect will be the foundation of what comes next. So in that sense, 400G per lane is not starting from scratch, but it also cannot skip over the lessons being learned at 200G. So this next generation will inherit not only the progress, but also the cold, hard realities that emerge when these high-speed interfaces move from theory into products into final deployments. Now, at the physical air, the central challenge that we're facing at these higher rates is shrinking system margin. As the data rates climb, every single part of the channel becomes more stressed. For example, the package escape, the board routing, connectors, cables, module interfaces, equalization, clocking recovery, just the calibration itself. Those are all much more complicated.

Things like loss, reflection, cross-talk, skew noise, even manufacturing. manufacturing variation of all these components becomes much more punishing and difficult. That means that the traditional approach of optimizing each subcomponent independently of the others becomes less effective. So I expect at 400 G per lane rates, a successful deployment and successful specification will require tighter co-designed. of all these different elements, whether it be the silicon, the packaged board connector, all of this stuff together, because the total margin available to absorb mismatches

and the imperfections becomes extremely small. Now adding into this, we have things like board error correction and signal processing that are also part of the challenge. These higher data rates tend to push the ecosystem towards stronger correction schemes and more sophisticated equalization and signal processing. But that comes with tradeoffs in terms of latency, complexity, power, implementation cost, etc. Those aspects are extremely important for AI and HPC systems because the network

is often part of a tightly synchronized fabric where both latency and throughput matter and industry operators have to balance the robustness against deployment realities. I'll add to this, a further complication is that this transition, this inflection is happening at the same time the industry is rethinking interconnect architecture more broadly. For example, pure electrical scaling is becoming harder. Cables are harder.

Back planes are harder. Electrical interconnects are harder. Therefore, shorter-reach optics, things like linear optics, co-package optics and other hybrid optical electrical strategies are moving from future concepts towards more practical system options, right? They're becoming more viable. And what that means is the question is no longer, can we make the next electrical link work, but also what parts of the system should remain electrical and which parts of the system should migrate to optical to get the best overall result? So I hope that the listener takes away that 400 G per lane is not blocked by one single problem. It's a challenge involving multiple different factors like margin, power,

manufacturerability, interoperability, and architecture all at once. Interesting. So as companies plan next generation AI and HPC systems, what decisions do they need to make today, even before the standards are finalized. Yes. How do we get the work done before it's finalized? Companies are planning next generation AI and HPC systems to make several important decisions now

before the standards are getting started because architecture choices that they make now will influence strongly what can be built later. The most important input that they can provide right now is clarity on system requirements, such as how much bandwidth is needed. What does the topology look like? Where are the system sensitivities? How far must the interconnects reach?

What tradeoffs are you willing to make or consider on the table as acceptable? Those choices determine what technical decisions matter most and help guide where the ecosystem and industry partners should prioritize flexibility versus a specific optimization. For example, companies need to think about whether they're optimizing for very dense scale up fabrics or broader scale out networks or some combination of the two. And you decide how much flexibility they want in lane aggregation and breakout. How much physical reach is, is, really required support a tray or a rack or a row or the whole cluster. And how much risk are they willing to take on new and emerging technologies and packaging or optics?

These are not procurement questions per se, but they are aspects that shape the silicon partitioning. the choices and interconnect, thermals, poor architecture, and the mechanical design. And that's why this early engagement matters so much. Standards group can define the framework, but they need concrete input and as much clarity as possible from the system builders and the end operators in order to understand

where the real constraints are and where tradeoffs are, acceptable. If the people deploying these systems can articulate their use cases and their pain points today, I expect that the specification development teams will focus on producing a healthy ecosystem and a variety of solutions that aligns with the deployment needs rather than idealized assumptions. So the short version is before the standards are complete, companies and in-operators need to give guidance on the architectural questions that they face. The more they can share their understanding of workload communication patterns, topologies, system-level trade-offs, risks they're willing to take, that's valuable information. The earlier those decisions are made and communicated, the better position, the standards, efforts, and the whole supplier ecosystem will be able to support these successful deployments on a timeline in which these solutions are needed. So, final question, Kent. As the ecosystem move forward, what role is synopsis playing in helping customers interpret the standards direction and get ready for,

early deployment. Daniel, one of the greatest strengths of the Ethernet ecosystem is the broad interoperability across a diverse supplier base. And this is where Synopsis in particular provides practical value to customers preparing for the next transition. The role is not simply to wait for the final standard and then react. The role of synopsis is to help customers understand where the standard direction is heading. What assumptions are becoming stable, which ones are not stable, and how to make design choices today that leave room for flexibility tomorrow. And that includes helping customers think through the relationship between two energy-per-lane technology of today, for energy-plean technology, for tomorrow system targets and the past towards future deployments.

So in practical terms, that means enabling customers to evaluate trade-offs early, how to design with our current 224 gig Ethernet Phi solutions, how to support these new 800 G and 1.60 architectures, and how flexibility in the silicon and end to end systems come together such that future standards evolution does not force an unnecessary redesign for the customer. Interoperability events and collaboration are especially important because they expose real system issues and gaps that do not always appear in an isolated operation or in the lab.

And those learnings are needed to be fed back into design decisions, implementation strategy, and ultimately the final product. Now, for example, synopsis has continued to commit to demonstrations of interoperability and design performance at events such as the OIF interoperability events, the Ethernet Alliance, plug-fests, even working directly with end customers and partners. The broader message that I want people to take away is that customers do not need to wait for every detail of a standard to settle before moving forward. They need informed guidance, and they need that guidance from a trusted partner on what is mature enough to adopt. What should remain flexible or configurable and where interoperability and margin from the ecosystem can reduce risk?

And synopsis helps bridge that gap between the standards direction, that direction that it's taking and the deployment reality by bringing silicon-proven IP, interoperability experience and insight into the whole system that can help customers prepare earlier and deliver a final product with more confidence. Great conversation, Kent. Thank you again for your time, and hopefully we can speak again or later this year. Thank you very much, Daniel, for the opportunity to come and speak. I enjoy the chance to give an update. That concludes our podcast. Thank you all for listening and have a great day.