SemiWiki.com - Video EP2: A Detailed Look at the Most Effective Way to Conquer Clock Jitter with Samia Rashid

Episode Date: March 14, 2025

In this episode of the Semiconductor Insiders video series, Dan is joined by Samia Rashid, co-founder and president of Infinisim. Samia provides detailed background on clock jitter – what it is, what causes it and the various methods to address the problem. Samia describes the unique clock analysis technology developed… Read More

Hello, my name is Daniel Nennie, the founder of SemiWiki, the open forum for semiconductor professionals. Welcome to the Semiconductor Insiders video series, where we take 10 minutes to discuss leading edge semiconductor design challenges with industry experts. Thank you for spending time with us today, Samia. It's my pleasure, Dan. I'm glad to be talking to you. Today we're going to talk about clock jitter. Samia, can you tell us what clock jitter is? Sure, Dan.

As you know, the clock is the most important signal. It is the heartbeat of digital circuits. It drives everything and keeps the system in sync. In an ideal world, clock signals would follow a perfectly precise timing pattern, but in reality, they don't. Tiny variations creep in, and those timing deviations are what we call clock jitter. So in other words, the clock edges, which is when signals rise and fall, aren't always exactly where they should be, or they're shifting slightly from cycle to cycle. So any deviation between the ideal and actual timing of the clock signal is clock

jitter. And when precision matters even the smallest shifts can have a big impact affecting the entire circuits performance. And so what causes clock jitter? Well there are many culprits, but I'll talk about two of the biggest ones. First one is PLL jitter. It is introduced at the clock source. Now what's interesting about this is that a PLL jitter is pretty much the same throughout the whole circuit.

And it affects the entire clock network uniformly. It's quite predictable. And since it is predictable, we can analyze it separately during the PLL design phase. The one that is far more tricky than is PDN or Power Delivery Network Induced Jitter. The source of this is a noisy supply voltage. This is tricky to analyze because it varies across different parts of the chip, because during signal propagation, gate currents change. Each gate in the clock network therefore experiences different levels of power supply noise,

causing unpredictable variations in timing. This means you can't just analyze the clock circuit on its own, you have to evaluate the power delivery network alongside it. That's the real challenge designers face and that's what people worry about and that's where we need to focus. Interesting.

What type of chip failures will you see due to clock jitter? Okay, so when a circuit is driven by a precise clock, everything runs smoothly. failures will you see due to clock jitter? Okay, so when a circuit is driven by a precise clock, everything runs smoothly. This means signals arrive at the right place at the right time with no setup, hold, or timing violations. Now remember, jitter eats into the timing window that is available for a digital signal to travel between the launch and capture plots. At smaller process nodes, JITTER can consume a significant portion of the timing budget, making it a major design concern. If JITTER becomes excessive, the circuit's behavior turns unpredictable.

You might see random glitches or intermittent failures because signals just don't have enough time to propagate. In extreme cases, like some we've seen in the news recently, clock jitter can trigger catastrophic failures and causing the chip to stop functioning entirely. So its impact can range anywhere from minor reliability issues to full system crashes. And how do designers handle clock jitter today? Well, there are two main approaches. First, you can perform a detailed timing analysis

to compute jitter. You can do this using conventional tools like Spice. While Spice can give you picosecond accuracy, and by the way, that is the level of accuracy that is needed to analyze clock jitter, the problem with SPICE is it can take forever to run. And this makes this approach impractical for most design teams. You just don't have enough time in the design cycle to do that.

The other approach is to add timing margins, basically extra time buffer to make sure the circuit still works even with some jitter. And yes this will help avoid jitter related issues but it comes at a big cost. One is performance hit. Your chip will run slower than it needs to so competitors who optimize their margins can push for higher performance. That puts you at a disadvantage. The second of course is wasted resources. We all know Dan that advanced semiconductor nodes are extremely expensive and if you're leaving too much margin you're not fully leveraging the speed and efficiency that you're paying for. That's money left on

the table and a direct hit to both profitability and competitiveness. And what is the right way to analyze clock jitter? Sure. Rather than relying on excessive timing margins, the smarter move is to calculate jitter precisely with picosecond accuracy, but in a practical time frame. An accurate jitter analysis will help you optimize timing where it truly matters.

And that's exactly what Infinison does. We have a patented technology that delivers spice level accuracy at a fraction of the runtime, giving designers deep real-time insights into clock behavior without slowing down the design process. As you can see in the picture, our solution provides you jitter at every gate for each clock cycle using multiple noise profiles. When you get this level of detailed analysis, you can essentially take out all the guesswork

or overly conservative margins. Instead, you can fine tune timing based on accurate data. That ensures maximum performance while still keeping your design rock solid. Bottom line, you're not leaving performance on the table. You're unlocking the full potential of your design without sacrificing reliability. Great discussion. Thank you, Samuel. Just one final question. Can you give us the elevator pitch for Infinisim? Of course, Dan. At Infinisison, we do one thing and we do it better than anyone else, and that is clock analysis. Clocks are our sole focus and accuracy is our holy grail.

We give designers the confidence to sign off on SOCs by delivering spice-level precision without the painfully long run times. Our baseline solution is targeted towards high-performance clocks. It provides a complete accurate picture of timing and electrical behavior of the entire clock network. And then we have clock aging analysis, and this predicts how stress-induced degradation will impact clock performance over time,

ensuring long-term reliability. And something like this is very important to the auto industry. stress-induced degradation will impact clock performance over time, ensuring long-term reliability. And something like this is very important to the auto industry. And of course what we talked about today, clock jitter analysis that delivers sub-peak of second accuracy in analyzing power supply induced jitter, so that designers can pinpoint hotspots and minimize the impact of those hotspots. Look down, clock timing issues can cripple a chip, whether at launch or years down the road. We help companies stay ahead of these challenges

and we help them unlock the full potential of their designs. I like to believe that when it comes to clock, infimism is the gold standard. And how do people normally contact you? You can of course contact us through our website at www.infinisim.com. Perfect. Thank you for your time today, Samia. Of course, Dan. My pleasure. That concludes our video. Thank you for watching and have a nice day.