SemiWiki.com - Video EP8: How Defacto Technologies Helps Customers Build Complex SoC Designs

Episode Date: June 6, 2025

In this episode of the Semiconductor Insiders video series, Dan is joined by Chouki Aktouf, CEO and Founder of Defacto Technologies. Dan explores the challenges of building complex SoCs with Chouki, who describes challenges around managing complexity at the front end of the process while staying within PPA requirements and … Read More

Hello, my name is Daniel Nenne, the founder of SemiWiki, the open forum for semiconductor professionals. Welcome to the Semiconductor Insiders video series, where we take 10 minutes to discuss leading edge semiconductor design challenges with industry experts. In today's episode, we are looking into how to build complex SoC designs with Shuki Actu from DeF De facto Technologies. Shuki, what are the current challenges behind building complex SoCs at the front end? Yeah, hello. Indeed, the current challenges to build large chips is first of all to manage the complexity of the chips. doing this integration or this design faster and with as low cost as possible.

Managing the PPA, trying to deliver as soon as possible. This is the key challenge is to do faster with a lower cost, knowing that the complexity is increasing. So in the line, complexity behind the process and building system on chip, it's to have as minimum resources as possible, manage, for example, the complexity of the views. As we all know before sentences, we need to manage different formats.

We need to manage the RTL, all the formats to be ready for sentences like the UPFSDC, the IPXact, sometimes internal formats. So managing all this, building the chip, go with confidence to the logic sentences or to the RTL simulation. This is really the challenge to do this, for example, within a day.

Right. Well, when building a new SOC, an important part is reuse from previous projects. How does SOC Compiler help with this? Yeah, reusing data, IPs, design information from previous projects is key to decrease the cost, to go faster. So with the Factors, as we see, compiler, a user can provide all the information from previous projects, all the data, all the RTL, all the file list, et cetera. And the tool can help extracting design information, can help building templates from the previous project to the user to start adding more information. And this actually design, reuse, and extraction

doesn't manage only the RTL, but RTL plus collaterals. And if needed, the missing views are generated from scratch. For example, I extract all the RTL from previous IPs and I need for packaging reasons to generate IP exact views. So the tool helps in that. So this is typically how the tool helps reaching high design ratio, like it's a 96, 98% from previous projects

which can be significant in decreasing the cost. And how do you manage PPA with this design process? Oh, PPA is really key when building a chip, when realizing this SOC design assembly. First of all, the tool, the software from De facto provides the features and APIs to build the top level, make the assembly. This is the first step. So this is needed for either logic synthesis or simulation. Now, when this is done, this is not enough to manage the PPA. To manage the PPA, you will need to make sure that this RTL and collaterals are, for example, physically aware. For example, mimic the layout post placement and routing. Restructuring an RTL, for example, is key to make sure that this RTL will lead to better results when going to synthesis.

So all this kind of managing the views together and re-architecturing the design pre-synthesis either for clock reasons, power reasons, physical reasons, DFT reasons, all this is managed. And when you do so, you will definitely better manage, for example, the area, you will get better results. You can decrease the area by 10, 15% when restructuring, for example, the RTL with a design collateral as per synthesis. So really this is very important.

Otherwise you would need to generate so many configurations, do so many iterations between the back end and the front. We're seeing a trend with AI integration with EDA tools. What is the de facto AI strategy? AI really is the key. De facto is now providing AI-based capabilities. Just to let you know that AI capabilities that I would be summarizing are key, especially when you design large chips here.

Just I want to show you that you can use DeFacto really to get really very good performance when building the chip. This is important to shorten the turnaround time, shorten the design cycles. Now, on the AI side, what is provided in de facto as a compiler today is a kind of assistant to help generating scripts more rapidly than just writing them from scratch. So generating scripts, better use the tool, for example,

asking the tool about the best way to use it, best commands to consider, et cetera. So to increase the tool usability and improve the code generation process today, as we see compiler, especially with this new major release that will be announced, the DAC, the 11, that will be demonstrating this AI-based capability. So this is really key for, especially the users

who start using the tool, and even for experts who wanna really generate new scripts, that's very, very helpful. Yeah, so this is the way we consider AI today, and much more features are coming in 2025. We'll be announcing them during the second half of this year. That's great.

I'm looking forward to seeing that. So final question, Suki. Is the DeFacto SOC compiler more useful for small or big chip design companies? What do your customers look like? Yeah, good question. Yeah, we actually, the current users are mixed between major chip design companies,

major semiconductor companies, the top tier, all of them use DeFacto, but we do count also small companies. It depends actually on the size of the chip. If you need to build a chip, either by small company or big company, where you need to do it faster, as we said earlier, we do it with as less engineering

resources as possible with confidence. This is where actually the de facto as a compiler is useful. So I would say as the answer to your question, Daniel is both. And again, it's a matter of complexity, managing the complexity and facing this complexity increase by using this solution.

Thank you, Shuki, that great conversation. I really look forward to seeing you at the Design Automation Conference later this month. Thank you very much. Likewise, thank you, Daniel. That concludes our video. Thank you for watching and have a nice day.